Seoul National University · Engineering
Professor Byung-Gook Park's research lab specializes in next-generation nanoelectronics and emerging memory technologies, with a focus on resistive random-access memory (ReRAM) and tunneling field-effect transistors (TFETs). The lab explores CMOS-compatible fabrication processes, nanostructured electrodes (such as nano-cone silicon), and innovative material architectures—like double-layered silicon nitride (SiN) stacks—to achieve low-power, high-performance devices. Key research directions include enhancing device reliability, reducing switching voltage and current, and enabling energy-efficient neuromorphic computing through spike-based neural networks and advanced device simulation. The lab combines experimental fabrication with advanced TCAD simulations to optimize device performance and scalability.
Figures are computed from collected data and may differ slightly.
SiN <sub>x</sub> -based nano-structure resistive memory is fabricated by fully silicon CMOS compatible process integration including particularly designed anisotropic etching for the construction of a nano-cone silicon bottom electrode (BE). Bipolar resistive switching characteristics have significantly reduced switching current and voltage and are demonstrated in a nano-cone BE structure, as compared with those in a flat BE one. We have verified by systematic device simulations that the main ca
In order to overcome the small current drivability of a tunneling field-effect transistor (TFET), we have introduced a TFET with the SiGe body and elevated Si drain region. The proposed TFET features large on-current and lower subthreshold swing (SS) compared with the Si TFET. Also, by using elevated Si drain region, it is expected that ambipolar current can be suppressed. Through the technology computer aided design (TCAD) simulation, the characteristics of the proposed TFET have been investiga
Spiking neural networks (SNNs) have attracted many researchers' interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron. In SNNs, n
Here we demonstrate low-power resistive switching in a Ni/SiN<sub>y</sub>/SiN<sub>x</sub>/p<sup>++</sup>-Si device by proposing a double-layered structure (SiN<sub>y</sub>/SiN<sub>x</sub>), where the two SiN layers have different trap densities. The LRS was measured to be as low as 1 nA at a voltage of 1 V, because the SiN<sub>x</sub> layer maintains insulating properties for the LRS. The single-layered device suffers from uncontrollability of the conducting path, accompanied by the inherent ran
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