Jaejin Lee

In this paper, we present the design and implementation of an Open Computing Language (OpenCL) framework that targets heterogeneous accelerator multicore architectures with local memory. The architecture consists of a general-purpose processor core and multiple accelerator cores that typically do not have any cache. Each accelerator core, instead, has a small internal local memory. Our OpenCL runtime is based on software-managed caches and coherence protocols that guarantee OpenCL memory consist

This paper presents a helper thread prefetching scheme that is designed to work on loosely coupled processors, such as in a standard chip multiprocessor (CMP) system or an intelligent memory system. Loosely coupled processors have an advantage in that resources such as processor and L1 cache resources are not contended by the application and helper threads, hence preserving the speed of the application. However, interprocessor communication is expensive in such a system. We present techniques to

There have been strong demands for a fast and cycle-accurate virtual platforms in the embedded systems area where developers can do meaningful software development including performance debugging in the context of the entire platform. In this paper, we describe the design and implementation of a fast and cycle-accurate architecture simulator called FaCSim as a first step towards such a virtual platform. FacSim accurately models the ARM9E-S processor core and ARM926EJ-S processor's memory subsyst

A novel function for image watermarking is proposed. We show how the watermarking sequence can be used for correction of illegal modifications. To make this task possible, the parities generated by the conventional error control coding (ECC) technique is used for the watermarking sequence. Then, the receiver can correct any alterations by applying the ECC decoding. To increase the correction capability we also adopt a scrambling scheme before the encoding to change a burst type of content modifi

The Cell BE processor is a heterogeneous multicore that contains one PowerPC Processor Element (PPE) and eight Synergistic Processor Elements (SPEs). Each SPE has a small software-managed local store. Applications must explicitly control all DMA transfers of code and data between the SPE local stores and the main memory, and they must perform any coherence actions required for data transferred. The need for explicit memory management, together with the limited size of the SPE local stores, makes

Traditional compiler techniques developed for sequential programs do not guarantee the correctness (sequential consistency) of compiler transformations when applied to parallel programs. This is because traditional compilers for sequential programs do not account for the updates to a shared variable by different threads. We present a concurrent static single assignment (CSSA) form for parallel programs containing cobegin/coend and parallel do constructs and post/wait synchronization primitives.

A novel function for image watermarking is introduced. The proposed function gives a restoration/correction capability to image watermarking as well as the detection and localisation of alterations. The basic idea of the proposed watermarking technique is to adopt conventional error control coding techniques for generating a watermark.

In this paper, we propose a software shared virtual memory (SVM) system for heterogeneous multicore accelerator clusters with explicitly managed memory hierarchies. The target cluster consists of a single manager node and many compute nodes. The manager node contains a generalpurpose processor and larger main memory, and each compute node contains a heterogeneous multicore processor and smaller main memory. These nodes are connected with an interconnection network, such as Gigabit Ethernet. The

In-depth convergence analyses for neutronics/thermal-hydraulics (T/H) coupled calculations are performed to investigate the performance of nonlinear methods based on the Fixed-Point Iteration (FPI). Asimplified neutronics-T/H coupled system consisting of a single fuel pin is derived to provide a testbed. The xenon equilibrium model is considered to investigate its impact during the nonlinear iteration. Aproblem set is organized to have a thousand different fuel temperature coefficients (FTC) and

The methods and performance of a pin-level nuclear reactor core thermal-hydraulics (T/H) code ESCOTemploying the drift-flux model are presented. This code aims at providing an accurate yet fast corethermal-hydraulics solution capability to high-fidelity multiphysics core analysis systems targetingmassively parallel computing platforms. The four equation drift-flux model is adopted for two-phase calculations,and numerical solutions are obtained by applying the Finite Volume Method (FVM) and theSe

A novel function for image watermarking is proposed. We show how a watermarking sequence can be used for the correction of illegal modifications. To make this task possible, the parities generated by the conventional error control coding (ECC) technique are used for the watermarking sequence; then the receiver can correct any alterations by applying the ECC decoding to the received image data. To increase the correction capability, we also adopt a scrambling scheme prior to the encoding to chang

The erythrocyte sedimentation rate (ESR) is a non-specific blood test for determining inflammatory conditions. However, the long measurement time (60 min) to obtain ESR is an obstacle for a prompt evaluation. In this study, to reduce the measurement time of ESR, deep neural networks (DNNs) were applied to the sedimentation tendency of blood samples. DNNs using multilayer perceptron (MLP), long short-term memory (LSTM), and gated recurrent unit (GRU) were assessed and compared to determine a suit