The University of Tokyo · Engineering
Professor Masaharu Kobayashi's research lab specializes in next-generation semiconductor devices and materials for ultra-low power electronics, with a focus on ferroelectric and high-κ dielectrics, especially hafnia-based (HfO₂) materials. The lab pioneers innovative device architectures such as negative capacitance FETs, ferroelectric tunnel junctions, and Schottky barrier engineering in group IV semiconductors like germanium, aiming to enable sub-0.2V operation for energy-harvesting IoT applications. Key research directions include fundamental physics of ferroelectricity, interface engineering, and process integration for CMOS compatibility. The lab combines advanced simulation, experimental characterization, and novel fabrication techniques to push the limits of energy efficiency and performance in nanoscale transistors and memory devices.
Figures are computed from collected data and may differ slightly.
Schottky barrier height modulation in metal/Ge Schottky junction was demonstrated by inserting an ultrathin interfacial silicon nitride layer. The SiN interfacial layer suppressed strong Fermi level pinning in metal/Ge Schottky junction, which resulted in effective control of Schottky barrier height. Metal/SiN/Ge Schottky diode was systematically investigated in terms of SiN thickness dependence and metal work function dependence. At an optimal SiN thickness, Ohmic contact between metal and Ge w
We have proposed and investigated a super steep subthreshold slope transistor by introducing negative capacitance of a ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate insulator to a vertical tunnel FET for energy efficient computing. The channel structure and gate insulator are systematically designed to maximize the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</su
We have investigated device design of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectric tunnel junction (FTJ) memory. Asymmetry of dielectric screening property in top and bottom electrodes is the key for high tunneling electroresistance (TER) ratio. Thus, metal and semiconductor electrodes are proposed. There exists a design space of ferroelectric material parameters to achieve high TER ratio under the constraint of d
Internet-of-Things (IoT) technologies require a new energy-efficient transistor which operates at ultralow voltage and ultralow power for sensor node devices employing energy-harvesting techniques as power supply. In this paper, a practical device design guideline for low voltage operation of steep-slope negative-capacitance field-effect-transistors (NCFETs) operating at sub-0.2V supply voltage is investigated regarding operation speed, material requirement and energy efficiency in the case of f
GeO 2 was grown by a slot-plane-antenna (SPA) high density radical oxidation, and the oxidation kinetics of radical oxidation GeO2 was examined. By the SPA radical oxidation, no substrate orientation dependence of growth rate attributed to highly reactive oxygen radicals with low oxidation activation energy was demonstrated, which is highly beneficial to three-dimensional structure devices, such as multigate field-effect transistors, to form conformal gate dielectrics. The electrical properties
We have experimentally investigated the polarization-limited operation speed of Negative Capacitance FET (NCFET) through direct measurement of negative capacitance in transient behavior of ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capacitor and physics-based modeling, for the first time. Systematic analysis of frequency dependence and transient characteristics of ferroelectric HfO <sub xmlns:mml="http://www.w3.org/199
In today's highly information-oriented society, a continuously increasing number of computing devices are needed in the Internet-of-Things (IoT) era, from high-end servers in cloud to sensor node devices in edge. Under the constraint of power consumption, energy-efficient computing is necessary to enable low-power operation and implement emerging algorithms such as machine learning. A steep-subthreshold-slope (SS) transistor can be a next-generation device technology platform for highly energy-e
The effects of quantum confinement on transport properties of silicon nanowire metal-oxide-semiconductor field-effect transistors (FETs) and single-electron transistors are experimentally investigated. By carefully designing the channel width, the nanowire transistors operate as silicon nanowire FETs (SNWFETs) or single-charge transistors. Large quantum confinement in ultranarrow silicon nanowires plays a key role in these devices. We also adopt a special device configuration in which both n-typ
The purpose of this paper is to construct modulation spaces M p , q ( R d ) for general 0 < p , q ? 8 , which coincide with the usual modulation spaces when 1? p , q ? 8 , and study their basic properties including their completeness. Given any such that supp and , our modulation space consists of all tempered distributions f such that the (quasi)‐norm is finite.
Ferroelectric memory devices are expected for low-power and high-speed memory applications. HfO<sub>2</sub>-based ferroelectric is attracting attention for its CMOS-compatibility and high scalability. Mesoscopic-scale grains, of which size is almost comparable to device size, are formed in HfO<sub>2</sub>-based ferroelectric poly-crystalline thin films, which largely influences electrical characteristics in memory devices. It is important to study the impact of mesoscopic-scale grain formation o
We have shown a practical device design guideline for sub-0.2V ultra-low power, steep slope ferroelectric FET using negative capacitance (NC) focusing on operation speed, material requirement, and energy efficiency for the first time. The operation speed is determined by finite switching time of ferroelectric polarization. For low supply voltage and hysteresis-free design, there exists a ferroelectric material parameter window to maximize the benefit of steep slope by NC. By the optimized device
The synchrotron radiation photoemission spectroscopic study was conducted to (a) investigate the surface chemistry of In0.53Ga0.47As and In0.52Al0.48As postchemical and thermal treatments, (b) construct band diagram, and (c) investigate the interface property of HfO2∕In0.53Ga0.47As and HfO2∕In0.52Al0.48As. Dilute HCl and HF etch remove native oxides on In0.53Ga0.47As and In0.52Al0.47As, whereas in situ vacuum annealing removes surface arsenic pileup. After the atomic layer deposition of HfO2, na
We successfully demonstrated Schottky barrier height modulation in metal/Ge Schottky junction by inserting an ultrathin interfacial SiN layer. The SiN layer suppressed strong Fermi level pinning in metal/Ge junction, which resulted in effective control of the Schottky barrier height. We systematically investigated its physics, for the first time, and almost zero Schottky barrier height was successfully obtained for electrons. We applied this technology to metal source/drain Ge NMOSFET and achiev
HfO2-based ferroelectric (FE–HfO2) is a promising material for low-power and high-capacity memory technology. Since thinner ferroelectric films are required for low voltage operation, the impact of film thickness on the switching kinetics of FE–HfO2 needs to be studied in detail. In this paper, metal/ferroelectric/metal capacitors are fabricated with several thicknesses of HfZrO2 (HZO) films and characterized to study the switching kinetics based on the nucleation limited switching (NLS) model.
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