Rei Ueno

This paper presents a side-channel analysis (SCA) on key encapsulation mechanism (KEM) based on the Fujisaki–Okamoto (FO) transformation and its variants. The FO transformation has been widely used in actively securing KEMs from passively secure public key encryption (PKE), as it is employed in most of NIST post-quantum cryptography (PQC) candidates for KEM. The proposed attack exploits side-channel leakage during execution of a pseudorandom function (PRF) or pseudorandom number generator (PRG)

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a

This paper presents an efficient fuzzy extractor (FE) design for biased physically unclonable functions (PUFs). To remove entropy leak from helper data in an efficient manner, we propose a new debiasing method, namely biased masking (BM). The proposed scheme removes the entropy leak by applying artificial noise (i.e., biased mask) such that the resulting response is uniform, and the added noise is removed by ECC decoding at the reconstruction as well as PUF noise. In addition, BM-based debiasing

Abstract. This paper proposes a compact and efficient GF (28) inver-sion circuit design based on a combination of non-redundant and redun-dant Galois Field (GF) arithmetic. The proposed design utilizes redun-dant GF representations, called Polynomial Ring Representation (PRR) and Redundantly Represented Basis (RRB), to implement GF (28) in-version using a tower field GF ((24)2). In addition to the redundant rep-resentations, we introduce a specific normal basis that makes it pos-sible to map the

This paper presents a systematic design of tamper-resistant Galois-Field (GF) arithmetic circuits based on Threshold Implementation (TI) where a secret variable is represented with multiple variables, called shares, given by random numbers. TI is one of the countermeasures against Differential Power Analysis (DPA) on cryptographic hardware. The security order of TI depends on the number of shares. The minimum number of shares to be resistant dth-order DPA is said to be (d + 1). While the constru

This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) based on a polynomial ring (PR) representation, which is a redundant representation for GF arithmetic. The proposed method extends a graph-based circuit description, called a Galois-field arithmetic circuit graph (GF-ACG), which was originally proposed for no redundant GF arithmetic. First, the extension of a GF-ACG is applied to the design and verification of the PR-based GF arithmetic circuits.

This paper presents high throughput/gates Feistel network (FN)-based AES-OTR hardware architectures. AES-OTR is an authenticated encryption (AE) scheme as a block cipher mode of operation using AES. While AES-OTR is one of the most theoretically efficient AEs using AES and has superior features, its practical efficiency in hardware is unclear due to no known reports of its hardware implementation. In this paper, we present efficient AES-OTR hardware architectures. In contrast to conventional AE

This paper presents a provably secure, higher-order, and leakage-resilient (LR) rekeying scheme named LR Rekeying with Random oracle Repetition (LR4), along with a quantitative security evaluation methodology. Many existing LR primitives are based on a concept of leveled implementation, which still essentially require a leak-free sanctuary (i.e., differential power analysis (DPA)-resistant component(s)) for some parts. In addition, although several LR pseudorandom functions (PRFs) based on only

This paper presents an efficient approach to verifying higher-degree Galois-field (GF) arithmetic circuits. The proposed method describes GF arithmetic circuits using a mathematical graph-based representation and verifies them by a combination of algebraic transformations and a new verification method based on natural deduction for first-order predicate logic with equal sign. The natural deduction method can verify one type of higher-degree GF arithmetic circuit efficiently while the existing me

This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p≥3) arithmetic circuits, which can be efficiently implemented by multiple-valued logic circuits in addition to the conventional binary circuits. We then show the validity of

This article proposes a formal design system for automatically generating provably secure register transfer level description of cryptographic hardware based on generalized masking scheme. -Rosario Cammarota, Intel Labs -Francesco Regazzoni, University of Amsterdam and Università della Svizzera Italiana