[Paper Review] 3D integration and packaging for solid-state qubits

D. Rosenberg, Steven Weber+10 more|arXiv (Cornell University)|Jun 26, 2019

Electronic and Structural Properties of Oxides33 citations

TL;DR

The paper surveys 3D integration and packaging strategies to improve scalability, microwave control, and cryogenic performance of solid-state qubits, including flip-chip, air-bridge, and through-substrate via approaches, with attention to minimizing losses and spurious modes.

ABSTRACT

Developing a packaging scheme that meets all of the requirements for operation of solid-state qubits in a cryogenic environment can be a formidable challenge. In this article, we discuss work being done in our group as well as in the broader community, focusing on the role of 3D integration and packaging in quantum processing with solid-state qubits.

Motivation & Objective

• Motivate the need for scalable solid-state qubits in quantum computing and outline DiVincenzo criteria considerations.
• Evaluate packaging and 3D integration approaches to reduce interconnect crowding and improve microwave control.
• Identify methods to tailor the microwave environment and suppress spurious modes in cryogenic operation.
• Discuss signal routing strategies from qubits to room temperature and across multi-chip stacks.
• Highlight future directions for scaling up qubit processors with integrated packaging architectures.

Proposed method

• Discuss 3D integration as a solution to interconnect crowding in qubit arrays.
• Present superconducting air bridges and flip-chip bonding as ways to cross wires and connect layers.
• Describe superconducting through-substrate vias (TSVs) for vertical wiring and reduced loss.
• Use microwave simulations and resonator measurements to assess TSV transitions and losses (Q factors).
• Explain approaches to shield qubits from unintended modes using enclosures, caps, and multilayer constructs.
• Outline cryogenic interconnect platforms and the trade-offs of different routing schemes.

Experimental results

Research questions

• RQ1 How can 3D integration and packaging mitigate interconnect bottlenecks in solid-state qubit arrays?
• RQ2 What are the loss mechanisms associated with TSV transitions and how do they impact qubit coherence?
• RQ3 How can the microwave environment be engineered to minimize crosstalk and spurious modes in cryogenic packaging?
• RQ4 What are effective strategies for routing signals from qubits to room temperature in scalable systems?
• RQ5 What future packaging architectures enable scaling beyond hundreds of qubits?

Key findings

• Superconducting TSVs with compact cross-section can maintain low loss and high yield up to thousands of links.
• Flip-chip integration preserves qubit lifetimes comparable to single-chip implementations (~20 μs).
• Microwave TSV transitions can achieve simulated reflections better than -30 dB with appropriate CPW design, and resonator Q factors range from 100,000 to 300,000, indicating low loss.
• Ground-plane connections and via-based interposers can reduce spurious cavity modes and microwave crosstalk.
• Shielding enclosures and micromachined cavities show potential for isolating qubits and enabling high-Q storage modules.
• cryogenic control electronics (SFQ and cryogenic CMOS) offer paths toward scalable qubit control while addressing quasiparticle poisoning challenges.