[Paper Review] A Novel Interconnect Camouflaging Technique using Transistor Threshold Voltage

Jae-Won Jang, Swaroop Ghosh|arXiv (Cornell University)|May 7, 2017

Physical Unclonable Functions (PUFs) and Hardware Security12 references3 citations

TL;DR

This paper proposes a novel interconnect camouflaging technique that uses transistor threshold voltage to obscure interconnect connectivity, making reverse engineering extremely difficult. By employing threshold voltage-defined pass transistor multiplexers (muxes), the method achieves high security with minimal area, delay, and power overhead—reducing reverse engineering effort by up to 33% while maintaining nominal operation and reliability.

ABSTRACT

Semiconductor supply chain is increasingly getting exposed to variety of security attacks such as Trojan insertion, cloning, counterfeiting, reverse engineering (RE) and piracy of Intellectual Property (IP) due to involvement of untrusted parties. Camouflaging of gates has been proposed to hide the functionality of gates. However, gate camouflaging is associated with significant area, power and delay overhead. In this paper, we propose camouflaging of interconnects using multiplexers (muxes) to protect the IP. A transistor threshold voltage-defined pass transistor mux is proposed to prevent its reverse engineering since transistor threshold voltage is opaque to the adversary. The proposed mux with more than one input, hides the original connectivity of the net. The camouflaged design operates at nominal voltage and obeys conventional reliability limits. A small fraction of nets can be camouflaged to increase the RE effort extremely high while keeping the overhead low. We propose controllability, observability and random net selection strategy for camouflaging. Simulation results indicate 15-33% area, 25-44% delay and 14-29% power overhead when 5-15% nets are camouflaged using the proposed 2:1 mux. By increasing the mux size to 4:1, 8:1, and 16:1, the RE effort can be further improved with small area, delay, and power penalty.

Motivation & Objective

• Address the growing threat of IP piracy, counterfeiting, and reverse engineering in untrusted semiconductor supply chains.
• Overcome the limitations of gate-level camouflaging, which incurs high area, power, and delay overhead.
• Develop a low-overhead interconnect camouflaging method that preserves circuit functionality and reliability.
• Enable effective protection of intellectual property by increasing the effort required for reverse engineering.
• Ensure compatibility with standard design flows by operating at nominal voltage and adhering to conventional reliability limits.

Proposed method

• Propose a transistor threshold voltage-defined pass transistor multiplexer (mux) to camouflage interconnects.
• Use multiplexers with more than one input to hide the original net connectivity from adversaries.
• Leverage the opacity of transistor threshold voltage to prevent reverse engineering, as it is difficult to measure or extract.
• Implement a controllability and observability-based strategy to select nets for camouflaging.
• Apply a random net selection strategy to further increase reverse engineering complexity.
• Use 2:1, 4:1, 8:1, and 16:1 muxes to scale camouflaging efficiency and security, with increasing overheads.

Experimental results

Research questions

• RQ1 Can interconnect camouflaging using threshold voltage-defined pass transistors effectively increase reverse engineering effort?
• RQ2 How does the proposed method compare to gate-level camouflaging in terms of area, delay, and power overhead?
• RQ3 What is the trade-off between camouflaging strength and hardware overhead when scaling mux size?
• RQ4 Can the proposed technique maintain nominal operation and reliability under standard process conditions?
• RQ5 How effective is the combination of controllability, observability, and random net selection in maximizing camouflaging security?

Key findings

• Camouflaging 5–15% of nets using a 2:1 mux results in 15–33% area overhead, 25–44% delay overhead, and 14–29% power overhead.
• Increasing the mux size to 4:1, 8:1, and 16:1 further improves reverse engineering resistance with only marginal increases in overhead.
• The proposed method maintains operation at nominal voltage and complies with conventional reliability constraints.
• The use of threshold voltage-defined pass transistors ensures that the underlying transistor parameters remain opaque to adversaries.
• The combination of controllability, observability, and random net selection strategies significantly increases the complexity of reverse engineering.
• Simulation results confirm that the technique achieves strong security with minimal impact on performance and resource usage.