[Paper Review] A Race Track Trapped-Ion Quantum Processor

Steven A. Moses, Charles H. Baldwin+94 more|arXiv (Cornell University)|May 5, 2023

Quantum Information and Cryptography109 references19 citations

TL;DR

The paper introduces a race-track shaped trapped-ion QCCD quantum processor (H2) with 32 qubits, showcases system-level benchmarks (QV=2^16, mirror benchmarking, RCS), and discusses scalability upgrades.

ABSTRACT

We describe and benchmark a new quantum charge-coupled device (QCCD) trapped-ion quantum computer based on a linear trap with periodic boundary conditions, which resembles a race track. The new system successfully incorporates several technologies crucial to future scalability, including electrode broadcasting, multi-layer RF routing, and magneto-optical trap (MOT) loading, while maintaining, and in some cases exceeding, the gate fidelities of previous QCCD systems. The system is initially operated with 32 qubits, but future upgrades will allow for more. We benchmark the performance of primitive operations, including an average state preparation and measurement error of 1.6(1)$ imes 10^{-3}$, an average single-qubit gate infidelity of $2.5(3) imes 10^{-5}$, and an average two-qubit gate infidelity of $1.84(5) imes 10^{-3}$. The system-level performance of the quantum processor is assessed with mirror benchmarking, linear cross-entropy benchmarking, a quantum volume measurement of $\mathrm{QV}=2^{16}$, and the creation of 32-qubit entanglement in a GHZ state. We also tested application benchmarks including Hamiltonian simulation, QAOA, error correction on a repetition code, and dynamics simulations using qubit reuse. We also discuss future upgrades to the new system aimed at adding more qubits and capabilities.

Motivation & Objective

• Demonstrate a new race-track geometry trap design for scalable QCCD quantum computation.
• Benchmark primitive and system-level performance of the H2 processor across gates, measurement, transport, and memory errors.
• Assess application-relevant performance via Hamiltonian simulation, QAOA, error correction demonstrations, and dynamics with qubit reuse.
• Evaluate system-level benchmarks (mirror benchmarking, quantum volume, random circuit sampling) to quantify large-scale circuit capability.
• Discuss future hardware upgrades aimed at increasing qubit count and capabilities.

Proposed method

• Describe trap design with RF tunnels, electrode broadcasting, and MOT loading to improve loading rates and reduce control complexity.
• Implement QCCD operations with the DG gate zones for quantum gates and SPAM, using Mølmer–Sørensen 2Q gates and 1Q wrapper pulses.
• Use conveyor-belt electrode broadcasting to minimize DC control lines and enable scalable qubit transport.
• Employ 2D MOT-based loading of 171Yb+ and 138Ba+ ions and optical pumping for state initialization.
• Provide comprehensive component benchmarking (SPAM, 1Q/2Q RB, leakage, crosstalk) and system-level benchmarks (MB, QV, RCS).
• Utilize OpenQASM 2.0/QIR workflows with real-time classical compute for feed-forward and error-correction simulations.

Experimental results

Research questions

• RQ1 What are the achievable gate fidelities and SPAM error rates in the race-track QCCD geometry?
• RQ2 How does the H2 platform scale in qubit number while maintaining gate performance and transport efficiency?
• RQ3 Can system-level benchmarks (MB, QV, RCS) reach high-depth circuits with 32 qubits in this architecture?
• RQ4 What are the dominant error sources during transport, memory, and gating, and how do they scale with qubit count?
• RQ5 How effectively can classical-quantum interaction support real-time decision-making and error-correction in this setup?

Key findings

• Average state preparation and measurement error: 1.6(1) × 10^-3.
• Average single-qubit gate infidelity: 2.5(3) × 10^-5.
• Average two-qubit gate infidelity: 1.84(5) × 10^-3.
• System-level benchmarks show quantum volume up to QV = 2^16.
• Creation of 32-qubit entanglement in a GHZ state demonstrated.
• Mirror benchmarking indicates effective 2Q error per gate ε_eff^2Q ≈ 2.6(2) × 10^-3 at N=32, not increasing with qubit number.
• QRC benchmarks include QV=2^16, MB, and RCS with linear cross-entropy fidelity measurements.
• Demonstrated Hamiltonian simulation, QAOA, and error-correction demonstrations with qubit reuse; discussed scalability upgrades.