[Paper Review] Binary nullity, Euler circuits and interlace polynomials

Lorenzo Traldi|ArXiv.org|Mar 25, 2009

Geometric and Algebraic Topology17 references4 citations

TL;DR

This paper extends the Cohn-Lempel equality to undirected 4-regular graphs, linking circuit partitions to vertex-nullity interlace polynomials via binary matrix nullity over GF(2). It establishes that the interlace polynomial of a looped interlace graph is essentially the generating function for circuit partitions in an associated 4-regular graph, unifying concepts from graph theory, knot theory, and matroid invariants.

ABSTRACT

A theorem of Cohn and Lempel [J. Combin. Theory Ser. A 13 (1972), 83-89] gives an equality relating the number of circuits in a directed circuit partition of a 2-in, 2-out digraph to the GF(2)-nullity of an associated matrix. This equality is essentially equivalent to the relationship between directed circuit partitions of 2-in, 2-out digraphs and vertex-nullity interlace polynomials of interlace graphs. We present an extension of the Cohn-Lempel equality that describes arbitrary circuit partitions in (undirected) 4-regular graphs. The extended equality incorporates topological results that have been of use in knot theory, and it implies that if H is obtained from an interlace graph by attaching loops at some vertices then the vertex-nullity interlace polynomial $q_{N}(H)$ is essentially the generating function for certain circuit partitions of an associated 4-regular graph.

Motivation & Objective

• To generalize the Cohn-Lempel equality from 2-in, 2-out digraphs to undirected 4-regular graphs.
• To establish a connection between circuit partitions in 4-regular graphs and the vertex-nullity interlace polynomial.
• To show that the interlace polynomial of a looped interlace graph encodes the generating function for circuit partitions in an associated 4-regular graph.
• To unify topological invariants from knot theory with graph-theoretic polynomials via matrix nullity over GF(2).

Proposed method

• Define a generalized Cohn-Lempel equality for arbitrary circuit partitions in 4-regular graphs using topological and combinatorial properties.
• Use the interlace matrix $I(D,C)$ of a 2-in, 2-out digraph $D$ with respect to an Euler circuit $C$ to model vertex interlacement relations.
• Relate the number of circuits in a partition to the $GF(2)$-nullity of submatrices of the interlace matrix via the extended Cohn-Lempel formula.
• Construct the vertex-nullity interlace polynomial $q_N(H)$ for a looped interlace graph $H$ as a sum over subsets $S \subseteq V(H)$ weighted by $(y-1)^{\nu(I_S)}$.
• Apply the multivariate interlace polynomial $C(H)$ to encode circuit partitions with orientation consistency/consistency violations.
• Demonstrate that the multivariate interlace polynomial $C(H)$ of a looped interlace graph $H$ corresponds to the transition polynomial of the underlying 4-regular graph.

Experimental results

Research questions

• RQ1 How can the Cohn-Lempel equality be extended from directed 2-in, 2-out digraphs to undirected 4-regular graphs?
• RQ2 What is the relationship between circuit partitions in 4-regular graphs and the vertex-nullity interlace polynomial?
• RQ3 How do looped vertices in an interlace graph encode orientation inconsistencies in circuit partitions?
• RQ4 Can the multivariate interlace polynomial of a looped interlace graph be interpreted as a generating function for circuit partitions?
• RQ5 What is the role of $GF(2)$-nullity in characterizing the number of circuits in a partition of a 4-regular graph?

Key findings

• The extended Cohn-Lempel equality relates the number of circuits in any circuit partition of a 4-regular graph to the $GF(2)$-nullity of a submatrix derived from the interlace matrix.
• For a looped interlace graph $H$, the vertex-nullity interlace polynomial $q_N(H)$ is the generating function for circuit partitions of the associated 4-regular graph, with each partition weighted by $(y-1)^{\text{number of circuits} - 1}$.
• The multivariate interlace polynomial $C(H)$ of a looped interlace graph $H$ is equivalent to the transition polynomial of the underlying 4-regular graph, encoding circuit partitions with orientation consistency conditions.
• The extended Cohn-Lempel equality applies to arbitrary permutations, not just disjoint transpositions, generalizing earlier results.
• There exist 4-regular graphs (e.g., with all-ones interlace matrix) where no skew-symmetric rational matrix of the same nullity exists, showing limitations of skew-symmetric realizations.
• The interlace polynomial of a looped interlace graph captures the full structure of circuit partitions in the associated 4-regular graph, including orientation behavior at each vertex.