[Paper Review] Channel-Width Dependent Enhancement in Nanoscale Field Effect Transistor

Xihua Wang, Yu Chen+3 more|ArXiv.org|Feb 15, 2008

Nanowire Synthesis and Applications1 references3 citations

TL;DR

This paper demonstrates that reducing the channel width in nanoscale silicon nanowire field-effect transistors (FETs) significantly enhances device performance due to increased surface-to-volume ratio. Using a top-down fabrication approach with electron-beam lithography and atomic layer deposition of Al₂O₃, the authors show that transconductance per unit width increases by an order of magnitude (from 6.31 to 61.4 nS/μm) as width decreases from 400 nm to 100 nm, enabling ultrasensitive sensing and improved logic operation.

ABSTRACT

We report the observation of channel-width dependent enhancement in nanoscale field effect transistors containing lithographically-patterned silicon nanowires as the conduction channel. These devices behave as conventional metal-oxide-semiconductor field-effect transistors in reverse source drain bias. Reduction of nanowire width below 200 nm leads to dramatic change in the threshold voltage. Due to increased surface-to-volume ratio, these devices show higher transconductance per unit width at smaller width. Our devices with nanoscale channel width demonstrate extreme sensitivity to surface field profile, and therefore can be used as logic elements in computation and as ultrasensitive sensors of surface-charge in chemical and biological species.

Motivation & Objective

• To investigate the impact of nanowire channel width on the electrical characteristics of silicon nanowire FETs.
• To develop a CMOS-compatible, top-down fabrication method for precise control of nanowire dimensions and gate geometry.
• To demonstrate enhanced device performance through increased surface-to-volume ratio in 3D nanowire channels.
• To evaluate the feasibility of these devices for ultrasensitive biosensing and logic applications.
• To establish an analytical model that explains the width-dependent threshold voltage shift and transconductance enhancement.

Proposed method

• Fabrication of silicon nanowire FETs using electron-beam lithography on SOI wafers with 100 nm device layer thickness.
• Use of atomic layer deposition (ALD) to grow a 20 nm Al₂O₃ gate dielectric layer on all three surfaces (top and two sides) of the nanowire.
• Implementation of a three-terminal, top-gated configuration with the back gate floated or grounded to enable measurement of transfer characteristics.
• Measurement of I-V curves under reverse source-drain bias to analyze threshold voltage and transconductance behavior.
• Development of an analytical model based on Schottky barrier effects and effective surface-to-volume ratio to explain experimental data.
• Evaluation of performance using transconductance per unit width, defined as $ g_m = \mu C_{ox} \frac{W_{\text{eff}}}{L} V_{ds} $, with $ W_{\text{eff}} = (w + 2H) \times n $.

Experimental results

Research questions

• RQ1 How does reducing the nanowire width below 200 nm affect the threshold voltage in silicon nanowire FETs?
• RQ2 To what extent does the surface-to-volume ratio influence transconductance per unit width in 3D nanowire FETs?
• RQ3 Can a non-Ohmic contact in the device be shown to have negligible impact on sensing performance under small reverse bias?
• RQ4 How does gate dielectric thickness interact with nanowire width to affect device sensitivity and performance?
• RQ5 Can the observed width-dependent enhancement be explained by a consistent analytical model incorporating Schottky barrier effects?

Key findings

• The threshold voltage increases linearly with the effective surface-to-volume ratio $ A_{\text{sur}}/V_{\text{vol}} = \frac{w + 2H}{wH} $, confirming a strong width-dependent effect.
• Transconductance per unit width increases from 6.31 nS/μm to 61.4 nS/μm as the nanowire width decreases from 400 nm to 100 nm, representing a tenfold enhancement.
• The non-Ohmic contact resistance is much smaller than the nanowire resistance under small reverse bias, so it has minimal impact on device performance in sensing applications.
• Thicker gate dielectrics (e.g., 120 nm Al₂O₃) suppress surface effects, reducing sensitivity, especially in wider wires, while narrow wires retain reasonable performance.
• The combination of narrow 3D nanowire geometry and thin dielectric layer enables superior gate control and enhanced sensitivity, suitable for biosensing and logic.
• The analytical model based on Schottky barrier and surface-to-volume ratio provides a good fit to experimental data, validating the physical origin of the observed enhancement.