[Paper Review] Comparing ternary and binary adders and multipliers

Daniel Etiemble|arXiv (Cornell University)|Aug 20, 2019

Interconnection Networks and Systems3 references4 citations

TL;DR

This paper compares the hardware complexity of ternary and binary adders and multipliers using CNTFET technology, evaluating 1-bit and 1-trit full adders and multipliers. Despite ternary circuits requiring fewer input/output connections due to higher information density (M ≈ N/1.585), the significantly higher transistor count of ternary basic blocks—especially for carry generation and multiplication—results in greater area, delay, and power dissipation, making ternary arithmetic circuits less efficient than their binary counterparts.

ABSTRACT

While many papers have proposed implementations of ternary adders and ternary multipliers, no comparisons have generally been done with the corresponding binary ones. We compare the implementations of binary and ternary adders and multipliers with the same computing capability according to the basic blocks that are 1-bit and 1-trit adders and 1-bit and 1-trit multipliers. Then we compare the complexity of these basic blocks by using the same CNTFET technology to evaluate the overall complexity of N-bit adders and M-trit adders on one side, and NxN bit multipliers and MxM trits multipliers with M = N/IR (IR = log(3)/log(2) is the information ratio). While ternary adders and multipliers have less input and output connections and use less basic building blocks, the complexity of the ternary building blocks is too high and the ternary adders and multipliers cannot compete with the binary ones.

Motivation & Objective

• To evaluate whether ternary arithmetic circuits can outperform binary circuits in terms of hardware complexity, despite higher information density per wire.
• To compare the number of basic building blocks (1-bit/1-trit full adders and multipliers) required for equivalent computing capability.
• To analyze the transistor-level complexity of 1-trit and 1-bit full adders and multipliers using CNTFET technology.
• To assess the overall complexity of N-bit and M-trit adders and multipliers, with M = N / log₂(3) ≈ N / 1.585.
• To determine whether the reduced number of connections in ternary circuits compensates for the increased complexity of their basic components.

Proposed method

• Defined equivalent computing capability using the information ratio IR = log₃(2) ≈ 1.585, so M trits ≈ N bits.
• Compared 1-bit and 1-trit full adders and multipliers as fundamental building blocks for adders and multipliers.
• Used CNTFET-based transistor-level design to compute transistor counts (T) for 1-bit and 1-trit components.
• Analyzed three adder architectures: Carry Propagate Adder (CPA), Carry Look-Ahead Adder (CLA), and Carry Skip Adder (CSA), comparing their transistor counts.
• Evaluated multiplier complexity using Wallace tree reduction, comparing 8-bit binary and 5-trit ternary multipliers.
• Calculated total transistor counts for full adders, half adders, multipliers, and carry computation blocks in both binary and ternary designs.

Experimental results

Research questions

• RQ1 Can ternary adders with M ≈ N/1.585 trits achieve lower hardware complexity than N-bit binary adders?
• RQ2 How does the transistor count of a 1-trit full adder compare to that of a 1-bit full adder in CNTFET technology?
• RQ3 Does the reduced number of interconnections in ternary adders and multipliers compensate for the higher complexity of their basic blocks?
• RQ4 What is the relative transistor cost of carry computation in CLA and CSA architectures for ternary versus binary designs?
• RQ5 Do ternary multipliers with fewer partial products still result in lower overall complexity than binary multipliers when considering multiplier and reduction tree complexity?

Key findings

• The 1-trit full adder requires 100 transistors, compared to 18 for the 1-bit full adder, making it significantly more complex.
• The 1-trit multiplier requires 38 transistors, compared to 6 for the 1-bit multiplier, resulting in a 6.3× increase in complexity.
• Carry computation in 5-trit CLA requires 310 transistors, compared to 288 for 8-bit binary CLA, despite fewer stages.
• The 5-trit Wallace tree uses 34 ternary full adders and 14 ternary half adders, while the 8-bit binary tree uses 35 binary full adders and 18 half adders, but the higher complexity of ternary components dominates.
• Ternary multipliers require 950 transistors for 25 1-trit multipliers, while binary multipliers use only 384 transistors for 64 AND gates, resulting in a 2.47× increase in transistor count for ternary multipliers.
• Due to higher transistor counts in basic blocks and carry computation, ternary adders and multipliers have more internal connections, larger area, higher delay, and greater power dissipation than binary circuits with equivalent information throughput.