[Paper Review] CrossStack: A 3-D Reconfigurable RRAM Crossbar Inference Engine

Jason K. Eshraghian, Kyoung-Rok Cho+1 more|arXiv (Cornell University)|Feb 7, 2021

Advanced Memory and Neural Computing25 references4 citations

TL;DR

CrossStack proposes a 3D reconfigurable RRAM crossbar inference engine that operates in two modes: expansion mode, doubling input resolution and reducing IR drop by 22%, and deep-net mode, improving inference speed per 10-bit convolution by 29% through pipelined read/write operations. The design uses stacked Al/TiO₂/TiO₂₋ₓ/Al memristors with CMOS-memristor hybrid cells for mode control via a read-enable signal.

ABSTRACT

Deep neural network inference accelerators are rapidly growing in importance as we turn to massively parallelized processing beyond GPUs and ASICs. The dominant operation in feedforward inference is the multiply-and-accumlate process, where each column in a crossbar generates the current response of a single neuron. As a result, memristor crossbar arrays parallelize inference and image processing tasks very efficiently. In this brief, we present a 3-D active memristor crossbar array `CrossStack', which adopts stacked pairs of Al/TiO2/TiO2-x/Al devices with common middle electrodes. By designing CMOS-memristor hybrid cells used in the layout of the array, CrossStack can operate in one of two user-configurable modes as a reconfigurable inference engine: 1) expansion mode and 2) deep-net mode. In expansion mode, the resolution of the network is doubled by increasing the number of inputs for a given chip area, reducing IR drop by 22%. In deep-net mode, inference speed per-10-bit convolution is improved by 29\% by simultaneously using one TiO2/TiO2-x layer for read processes, and the other for write processes. We experimentally verify both modes on our $10 imes10 imes2$ array.

Motivation & Objective

• To address the growing demand for high-throughput, reconfigurable hardware accelerators for deep neural network inference beyond GPUs and ASICs.
• To overcome limitations in existing 3D RRAM arrays, which are mostly limited to digital memory and lack adaptability to evolving neural network architectures.
• To enable hardware reconfigurability for dynamic adaptation to new network topologies without redesign cycles.
• To reduce IR drop and improve inference speed through innovative 3D memristor crossbar architecture with dual operational modes.
• To demonstrate experimental feasibility of pipelined read and write operations in a 3D stacked RRAM array using CMOS-hybrid cell design.

Proposed method

• The CrossStack architecture uses a 3D stacked pair of Al/TiO₂/TiO₂₋ₓ/Al memristor crossbars with shared middle electrodes to enable dual-layer operation.
• It employs CMOS-memristor hybrid cells with a read-enable (RE) signal to control mode selection: high RE for expansion mode, low RE for deep-net mode.
• In expansion mode, both layers contribute to the same column current, effectively doubling the number of inputs per column and halving wire resistance.
• In deep-net mode, one layer is used for read operations while the other is used for write operations, enabling pipelined processing.
• The design leverages Kirchhoff’s Current Law and Ohm’s Law to perform analog matrix-vector multiplication via conductance-weighted current summation: i = V^i G.
• The system uses a 10×10×2 array fabricated in the SK Hynix 180nm CMOS process with independently controlled CMOS circuitry for each layer.

Experimental results

Research questions

• RQ1 Can a 3D stacked RRAM crossbar architecture be reconfigured to support two distinct inference modes for improved performance and scalability?
• RQ2 How can IR drop be reduced in high-density crossbar arrays without increasing chip area?
• RQ3 To what extent can pipelined read and write operations in a 3D RRAM array improve inference throughput?
• RQ4 What are the performance and reliability trade-offs of using single-bit memristors in a reconfigurable crossbar for analog inference?
• RQ5 How does the use of shared middle electrodes in a 3D memristor stack affect signal integrity and power efficiency?

Key findings

• Expansion mode doubles the number of inputs per column, reducing IR drop by 22% compared to an equivalent 2D array.
• Deep-net mode improves inference speed per 10-bit convolution by 29% by enabling simultaneous read and write operations across two isolated layers.
• Transient analysis shows a worst-case current deviation of 8% from the ideal value, indicating a practical limit of approximately 3.5 bits per memristor due to device variability.
• The 10ns read-out time is subsumed within the 25ns programming time in the conservative 1-bit-per-cell case, confirming the effectiveness of in-situ pipelining.
• Leakage currents and nonlinearity under high write voltages (VIN > 3V) were observed, but subthreshold leakage was minimal in the design.
• Capacitive coupling and thermal dissipation remain challenges in 3D integration, though wider metal layer spacing helps mitigate coupling risks.