[Paper Review] Cryo-CMOS Band-gap Reference Circuits for Quantum Computing

Yuanyuan Yang, Kushal Das+2 more|arXiv (Cornell University)|Oct 2, 2019

Advancements in Semiconductor Devices and Circuit Design51 references4 citations

TL;DR

This paper presents cryo-CMOS band-gap reference (BGR) circuits fabricated in 0.35 µm SiGe BiCMOS and 28 nm FDSOI CMOS processes, designed to deliver stable voltage and current references at deep-cryogenic temperatures (down to 4 K). The SiGe BGRs achieve 1.5–1.8 µW power consumption at 6 K, while MOS-only BGRs in FDSOI remain functional down to 4 K, demonstrating viable low-power, temperature-stable reference solutions for scalable quantum computing control interfaces.

ABSTRACT

The control interface of a large-scale quantum computer will likely require electronic sub-systems that operate in close proximity to the qubits, at deep cryogenic temperatures. Here, we report the low-temperature performance of custom cryo-CMOS band-gap reference circuits designed to provide stable voltages and currents on-chip, independent of local temperature fluctuations. Our circuits are fabricated in 0.35 um silicon Germanium (SiGe) BiCMOS and 28 nm Fully Depleted Silicon On Insulator (FDSOI) CMOS processes, and we compare the performance of each. Beyond their specific application as low-power references, these circuits are ideal test-vehicles for developing design approaches that mitigate the adverse effects of cryogenic temperatures on circuit performance.

Motivation & Objective

• Develop low-power, temperature-stable voltage and current references for cryogenic quantum computing control systems.
• Address the challenge of transistor behavior degradation at deep-cryogenic temperatures (e.g., carrier freeze-out, threshold voltage shifts).
• Evaluate and compare the performance of SiGe BiCMOS and FDSOI CMOS processes for cryogenic analog circuit design.
• Establish reference circuits as test-vehicles for cryogenic design techniques that mitigate temperature and process variations.
• Enable on-chip integration of stable references to reduce sensitivity to local temperature fluctuations in quantum control ASICs.

Proposed method

• Design two BGR topologies: a conventional current mirror BGR (SiGe BGR1) and a modified version (SiGe BGR2) using SiGe heterojunction bipolar transistors (HBTs).
• Implement MOS-only BGRs in 28 nm FDSOI CMOS using back-gate biasing and resistor trimming for calibration and stability.
• Use feedback-based band-gap reference architecture to cancel temperature-dependent voltage variations, leveraging the temperature coefficient of base-emitter voltage in BJTs.
• Apply resistor trimming with 6-bit binary-weighted resolution to calibrate output voltage and current independently.
• Employ back-gate control in FDSOI MOS transistors to tune threshold voltage and improve current mirror matching.
• Characterize circuits in cryogenic probe stations and dilution refrigerators across 4 K to 300 K, measuring output voltage, current, and offset characteristics.

Experimental results

Research questions

• RQ1 Can SiGe HBT-based band-gap references maintain functionality and stability at temperatures as low as 4 K?
• RQ2 How do MOS-only BGRs in 28 nm FDSOI CMOS perform at cryogenic temperatures, and can they be calibrated for precision?
• RQ3 To what extent do back-gate biasing and resistor trimming improve the accuracy and stability of cryogenic references?
• RQ4 How do process variations and temperature-dependent transistor behavior affect reference output in cryogenic regimes?
• RQ5 Can BGR circuits serve as effective test-vehicles for developing general cryogenic IC design techniques?

Key findings

• The SiGe BGRs in 0.35 µm BiCMOS process achieve 1.5 µW and 1.8 µW power consumption at 6 K, respectively, demonstrating low-power operation in cryogenic conditions.
• The MOS-only BGRs in 28 nm FDSOI CMOS remain functional down to 4 K, indicating viability of CMOS-based references at ultra-low temperatures.
• Back-gate biasing in FDSOI MOS transistors enables tuning of threshold voltage, reducing current mirror offset and improving matching at low temperatures.
• Resistor trimming with 6-bit resolution allows precise calibration of output voltage and current, with trimming codes inversely related to resistance values.
• The current mirror offset in the MOS-only reference reaches a peak of approximately 7.5% at 1.66 V back-gate bias, primarily due to MUX switch effects at high biases.
• Silicon BJT-based BGRs in 28 nm FDSOI fail around 40 K, indicating limitations of standard CMOS BJTs in deep-cryogenic operation.