[Paper Review] Cryogenic Characerization and Modeling of Standard CMOS down to Liquid Helium Temperature for Quantum Computing

Zhen Li, Chao Luo+4 more|arXiv (Cornell University)|Nov 28, 2018

Advancements in Semiconductor Devices and Circuit Design19 references4 citations

TL;DR

This paper presents a cryogenic characterization and compact SPICE modeling of 0.18 µm CMOS technology (1.8V and 5V) from 300 K down to 4.2 K, using BSIM3v3-based parameter extraction and a subcircuit model to correct the kink effect. The resulting model achieves sub-2% RMS error in I-V fitting at liquid helium temperature, enabling accurate simulation of cryogenic CMOS circuits for quantum computing control systems.

ABSTRACT

Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to 4.2K. A simple subcircuit was built to correct the kink effect. This work provides experimental evidence for implementation of cryogenic CMOS technology, a valid industrial tape-out process model, and romotes the application of integrated circuits in cryogenic environments, including quantum measurement and control systems for quantum chips at very low temperatures.

Motivation & Objective

• To enable reliable cryogenic CMOS circuit design for quantum computing by extending standard SPICE modeling to liquid helium temperatures.
• To systematically characterize 0.18 µm CMOS transistors (NMOS and PMOS) across varying W/L ratios and bias conditions from 300 K to 4.2 K.
• To extract and revise temperature-dependent SPICE model parameters for BSIM3v3 to accurately reflect cryogenic device behavior.
• To correct the kink effect in cryogenic I-V characteristics using a subcircuit with a nonlinear resistor model.
• To provide a validated, industrial-grade compact model for EDA tools to support tape-out of cryogenic integrated circuits.

Proposed method

• Conducted DC I-V measurements on 36 CMOS devices (various W/L, oxide thicknesses, and voltages) at temperatures from 300 K down to 4.2 K using a dipstick-based cryogenic setup with liquid helium and nitrogen.
• Used a custom cryogenic test setup with a vacuum-flanged steel pipe, DIP sockets, and Rh-Fe temperature sensors to enable stable low-temperature measurements.
• Extracted key device parameters (Vth, Ion/Ioff, Gm,max, resistivity) from measured data across the full temperature range.
• Revised BSIM3v3 model parameters using a semi-empirical, physics-guided extraction process with local optimization, focusing on threshold voltage, mobility, short-channel, and bulk effects.
• Implemented a subcircuit model with a nonlinear resistor in series with the substrate to correct the kink effect, with resistor values extracted via polynomial fitting in MATLAB.
• Evaluated model accuracy using RMS error between simulated and measured I-V curves, with Ith set to the maximum measured current.

Experimental results

Research questions

• RQ1 Can standard 0.18 µm CMOS technology be reliably characterized and modeled at temperatures as low as 4.2 K?
• RQ2 How do key MOSFET parameters (threshold voltage, on/off current ratio, transconductance) vary with temperature from 300 K to 4.2 K?
• RQ3 To what extent does the standard BSIM3v3 model fail at cryogenic temperatures, and how can it be corrected?
• RQ4 Can a subcircuit model with a nonlinear resistor effectively mitigate the kink effect in cryogenic CMOS devices?
• RQ5 Can the revised model achieve sufficient accuracy for use in EDA simulations of cryogenic integrated circuits?

Key findings

• The threshold voltage (Vth) and active area resistance of 0.18 µm CMOS were measured for the first time from 300 K down to 4.2 K.
• The RMS error between simulated and measured I-V characteristics was reduced from over 60% (default BSIM3v3) to less than 2% after parameter revision and kink correction.
• For thin-oxide NMOS (W/L = 10 µm/0.16 µm), the corrected model achieved 1.71% RMS error at 4.2 K under VBS = 0 V bias.
• For thick-oxide PMOS (W/L = 10 µm/10 µm), the corrected model achieved 0.96% RMS error at 4.2 K under VBB = 4 V bias.
• The kink effect, which causes deviations in I-V curves at low VDS, was effectively corrected using a subcircuit with a nonlinear resistor representing freeze-out effects in the LDD region.
• The resulting compact SPICE model is the first BSIM3v3-based model valid down to 4.2 K for standard CMOS, enabling direct use in EDA simulations for cryogenic IC design.