[Paper Review] Cryogenic silicon surface ion trap

Michael Niedermayr, Kirill Lakhmanskiy+5 more|arXiv (Cornell University)|Mar 20, 2014

Quantum Information and Cryptography36 references20 citations

TL;DR

This paper presents a cryogenic surface ion trap fabricated from intrinsic silicon using standard semiconductor processes, eliminating the need for a shielding ground plane. By operating at low temperatures, the trap achieves ultra-low RF losses and ion heating rates as low as 0.33 phonons/s, enabling long ion lifetimes and scalable integration with on-chip electronics and micro-optics for quantum information processing.

ABSTRACT

Trapped ions are pre-eminent candidates for building quantum information processors and quantum simulators. They have been used to demonstrate quantum gates and algorithms, quantum error correction, and basic quantum simulations. However, to realise the full potential of such systems and make scalable trapped-ion quantum computing a reality, there exist a number of practical problems which must be solved. These include tackling the observed high ion-heating rates and creating scalable trap structures which can be simply and reliably produced. Here, we report on cryogenically operated silicon ion traps which can be rapidly and easily fabricated using standard semiconductor technologies. Single $^{40}$Ca$^+$ ions have been trapped and used to characterize the trap operation. Long ion lifetimes were observed with the traps exhibiting heating rates as low as $\dot{\bar{n}}=$ 0.33 phonons/s at an ion-electrode distance of 230 $μ$m. These results open many new avenues to arrays of micro-fabricated ion traps.

Motivation & Objective

• Address the challenge of high ion heating rates in scalable ion trap architectures.
• Overcome RF power dissipation in silicon substrates at room temperature by leveraging cryogenic operation.
• Enable scalable, micro-fabricated ion traps using standard semiconductor techniques without requiring shielding electrodes.
• Facilitate integration with on-chip electronics, micro-optics, and sensors for a quantum lab-on-a-chip.
• Demonstrate a simple, reliable fabrication process compatible with VLSI and high-throughput production.

Proposed method

• Fabricated planar surface ion traps using high-resistivity float-zone silicon wafers (ρ > 5000 Ω·cm).
• Employed standard optical lithography and deep reactive ion etching to pattern electrodes with 10 µm gaps and ~100 µm depth.
• Deposited Ti/Au electrodes via electron-beam evaporation without post-deposition cleaning.
• Used thermal oxidation (2 µm SiO₂) to prevent metal diffusion into silicon.
• Integrated the trap with an LC resonator (20.6 MHz at 10 K) and capacitive voltage divider for RF voltage monitoring.
• Implemented cryo-compatible DC filters (RC and surface-mount) with 4.8 kHz cut-off to suppress RF noise on DC lines.

Experimental results

Research questions

• RQ1 Can intrinsic silicon be used as a substrate for cryogenic surface ion traps without a shielding ground plane?
• RQ2 What is the ion heating rate in a cryogenically operated intrinsic silicon trap at 4 K?
• RQ3 Can standard semiconductor fabrication techniques be applied to produce scalable, low-loss ion traps?
• RQ4 How does cryogenic operation reduce RF losses and ion heating in silicon-based traps?
• RQ5 To what extent can on-chip integration of electronics and optics be enabled by eliminating the ground plane?

Key findings

• The trap achieved a record-low ion heating rate of 0.33 phonons per second at an ion-electrode distance of 230 µm.
• Single 40Ca⁺ ions were stably trapped and characterized, demonstrating long ion lifetimes at cryogenic temperatures.
• The absence of a shielding ground plane enabled simpler fabrication and full compatibility with through-wafer vias and micro-optical features.
• The use of intrinsic silicon at 4 K resulted in negligible RF losses due to charge carrier freeze-out, eliminating the need for doped silicon or shielding.
• The LC resonator operated at 20.6 MHz with a Q-factor suitable for precise RF voltage measurement at 10 K.
• Cryo-compatible DC filters with 4.8 kHz cut-off effectively suppressed RF noise on DC lines, ensuring stable trap operation.