[Paper Review] Design of a Superconducting Multiflux Non-Destructive Readout Memory Unit

Beyza Zeynep Ucpinar, Yasemin Kopur+3 more|arXiv (Cornell University)|Sep 26, 2023

Semiconductor materials and devices4 citations

TL;DR

This paper proposes a superconducting Non-Destructive Readout (NDRO) memory unit with single- and multi-fluxon storage capabilities using a local feedback wiring structure based on Rapid Single Flux Quantum (RSFQ) technology. The design achieves 10GHz operation with 64% margin for 1-bit NDRO and 20% for 2-bit M-NDRO, enabling high-density, high-speed cryogenic memory with minimal refresh overhead by leveraging ultrafast SFQ pulse propagation and optimized Josephson transmission lines.

ABSTRACT

Due to low power consumption and high-speed performance, superconductor circuit technology has emerged as an attractive and compelling post-CMOS technology candidate. However, the design of dense memory circuits presents a significant challenge, especially for tasks that demand substantial memory resources. While superconductor memory cells offer impressive speed, their limited density is the primary yet-to-be-solved challenge. This study tackles this challenge head-on by introducing a novel design for a Non-Destructive Readout (NDRO) memory unit with single or multi-fluxon storage capabilities within the same circuit architecture. Notably, single storage demonstrates a critical margin exceeding 20\%, and multi-fluxon storage demonstrates 64\%, ensuring reliable and robust operation even in the face of process variations. These memory units exhibit high clock frequencies of 10GHz. The proposed circuits offer compelling characteristics, including rapid data propagation and minimal data refreshment requirements, while effectively addressing the density concerns associated with superconductor memory, doubling the memory capacity while maintaining the high throughput speed.

Motivation & Objective

• Address the challenge of low memory density in superconductor circuits, a key bottleneck for post-CMOS computing.
• Develop a scalable, high-speed memory architecture compatible with cryogenic computing systems.
• Enable non-destructive readout with minimal refresh requirements to improve efficiency and throughput.
• Design a unified circuit architecture supporting both 1-bit and 2-bit storage via parameter variation.
• Achieve robust operation under process variations through high design margins.

Proposed method

• Implement a local feedback wiring structure using Josephson Transmission Lines (JTL), Splitters (SPL), and Confluence Buffers (CBU) to enable rapid data reloading after readout.
• Use a single fluxon to represent 1 bit in the NDRO cell, and three fluxons to represent 2 bits in the M-NDRO cell via a Multiple-Clock Generator (MCG) and Reset Generator (RG).
• Leverage the intrinsic speed of SFQ pulses to minimize data refresh time, relying on CBU timing for recovery.
• Optimize fundamental wiring cells (JTL, SPL, CBU) for minimal propagation delay to support 10GHz operation.
• Apply parameter tuning in the storage loop to enable different fluxon storage levels without architectural changes.
• Use qCS software for margin analysis to evaluate robustness against process variations.

Experimental results

Research questions

• RQ1 Can a single superconducting circuit architecture support both 1-bit and 2-bit non-destructive readout memory with high reliability?
• RQ2 How can local feedback wiring minimize refresh time and enable high-speed operation in superconducting memory?
• RQ3 What are the achievable design margins for 1-bit and 2-bit NDRO cells under process variation?
• RQ4 Can multi-fluxon storage be implemented efficiently in a scalable, cryogenic memory design?
• RQ5 To what extent does the use of a Multiple-Clock Generator and Reset Generator enable counter-like functionality in the M-NDRO cell?

Key findings

• The 1-bit NDRO memory unit achieves a critical margin of 64%, indicating strong resilience to process variations.
• The 2-bit M-NDRO memory unit achieves a 20% margin, demonstrating robustness despite increased complexity.
• Both memory units operate at a maximum clock frequency of 10GHz, enabling high-throughput data processing.
• The local feedback wiring structure enables near-instantaneous data reloading, reducing refresh overhead to negligible levels.
• The M-NDRO circuit successfully demonstrates increment and decrement operations via set and reset signals, functioning as a flux-based counter.
• The proposed architecture doubles memory capacity compared to single-fluxon designs while maintaining high speed and low power, due to shared wiring and scalable parameter tuning.