[Paper Review] Designing fault-tolerant circuits using detector error models

Peter-Jan H. S. Derks, Alex Townsend-Teague+2 more|arXiv (Cornell University)|Jul 18, 2024

Radiation Effects in Electronics4 citations

TL;DR

This paper introduces detector error models (DEMs) as a powerful framework for designing fault-tolerant quantum circuits across three abstraction levels: syndrome extraction, measurement scheduling, and logical gate gadgets. It demonstrates improved resilience to measurement errors in surface codes, shorter measurement schedules for color codes, and a more efficient fault-tolerant logical measurement procedure, all verified via DEM-based analysis and simulations under realistic noise models.

ABSTRACT

Quantum error-correcting codes, such as subspace, subsystem, and Floquet codes, are typically constructed within the stabilizer formalism, which does not fully capture the idea of fault-tolerance needed for practical quantum computing applications. In this work, we explore the remarkably powerful formalism of detector error models, which fully captures fault-tolerance at the circuit level. We introduce the detector error model formalism in a pedagogical manner and provide several examples. Additionally, we apply the formalism to three different levels of abstraction in the engineering cycle of fault-tolerant circuit designs: finding robust syndrome extraction circuits, identifying efficient measurement schedules, and constructing fault-tolerant procedures. We enhance the surface code's resistance to measurement errors, devise short measurement schedules for color codes, and implement a more efficient fault-tolerant method for measuring logical operators.

Motivation & Objective

• To address the lack of a standardized, decoder-ready format for representing fault-tolerant quantum circuits.
• To demonstrate that detector error models (DEMs) provide a unified, information-rich framework for verifying error-correcting capabilities at all levels of circuit abstraction.
• To design and optimize syndrome extraction circuits, measurement schedules, and logical gadgets using DEMs, improving resilience and efficiency under realistic noise.
• To show that DEMs enable systematic, scalable design of fault-tolerant procedures across different quantum error-correcting codes.

Proposed method

• The authors formalize detector error models (DEMs) as a circuit-level representation that encodes all relevant error propagation and detection information for Clifford circuits.
• They use DEMs to analyze and optimize syndrome extraction circuits for the surface code under measurement-biased noise, achieving twice the tolerance to measurement errors.
• A systematic method is developed to generate compact measurement schedules for color codes by modeling detector dependencies and error propagation.
• A new fault-tolerant logical measurement gadget is designed using error-detection-based verification, reducing time overhead compared to standard methods.
• The framework is applied to three levels of abstraction: syndrome extraction (circuit level), measurement scheduling (timing), and logical gadgets (high-level operations).
• Simulations under realistic noise models—including superconducting-inspired and measurement-biased noise—validate the performance improvements.

Experimental results

Research questions

• RQ1 How can detector error models be used to systematically design syndrome extraction circuits that are more resilient to measurement errors?
• RQ2 What is the optimal measurement schedule for color codes that minimizes circuit depth while maintaining fault tolerance?
• RQ3 Can a more efficient fault-tolerant logical measurement gadget be constructed using DEMs to reduce time overhead?
• RQ4 How does the structure of a detector error model influence the logical error rate of a circuit?
• RQ5 Can DEMs serve as a universal, standardized interface between circuit designers and decoders in quantum error correction?

Key findings

• The proposed syndrome extraction circuits for the surface code tolerate twice as many measurement errors as conventional designs under measurement-biased noise.
• For the distance-3 and distance-5 triangular color codes on a hexagonal lattice, the new measurement schedules are shorter than previously known schedules.
• The new fault-tolerant logical measurement gadget reduces time overhead by using error detection instead of full syndrome measurement, improving efficiency.
• The DEM-based framework enables the identification of logical error thresholds and error propagation paths, allowing for targeted circuit optimization.
• Simulations show that the new circuits maintain low logical error rates in memory and stability experiments under realistic noise models.
• The study demonstrates that DEMs can unify and streamline the design process across all levels of fault-tolerant circuit abstraction.