[Paper Review] Digital-analog quantum simulation of fermionic models

Lucas C. Céleri, Daniel Huerga+4 more|arXiv (Cornell University)|Mar 29, 2021

Quantum Computing Algorithms and Architecture4 citations

TL;DR

This paper proposes a digital-analog quantum algorithm for simulating fermionic Hamiltonians, including the 1D Fermi-Hubbard model, using a hybrid approach that combines digital quantum gates with analog evolution blocks to enhance coherence and reduce gate count. The method achieves high-fidelity simulation with reduced SWAP gates and improved performance in a codesigned architecture, demonstrating robustness against noise and scalability advantages over purely digital approaches.

ABSTRACT

Simulating quantum many-body systems is a highly demanding task since the required resources grow exponentially with the dimension of the system. In the case of fermionic systems, this is even harder since nonlocal interactions emerge due to the antisymmetric character of the fermionic wave function. Here, we introduce a digital-analog quantum algorithm to simulate a wide class of fermionic Hamiltonians including the paradigmatic one-dimensional Fermi-Hubbard model. These digital-analog methods allow quantum algorithms to run beyond digital versions via an efficient use of coherence time. Furthermore, we exemplify our techniques with a low-connected architecture for realistic digital-analog implementations of specific fermionic models.

Motivation & Objective

• To develop a digital-analog quantum algorithm for simulating strongly correlated fermionic systems, particularly the 1D Fermi-Hubbard model.
• To reduce the resource overhead associated with fermionic simulations, especially the high number of SWAP gates required in digital quantum circuits.
• To improve simulation fidelity and coherence time utilization by integrating analog evolution blocks with digital gate sequences.
• To evaluate the algorithm's performance under realistic noise conditions, including decoherence, gate errors, and timing jitter.
• To demonstrate the scalability and robustness advantages of digital-analog quantum computation (DAQC) over purely digital approaches in NISQ devices.

Proposed method

• The algorithm employs a symmetric Lie-Suzuki-Trotter decomposition to approximate the time evolution of the fermionic Hamiltonian, minimizing Trotter error with negligible additional cost.
• It combines digital single-qubit and two-qubit gates with long-duration analog evolution blocks governed by an Ising-type Hamiltonian, enabling efficient simulation of non-local fermionic interactions.
• A 1D nearest-neighbor and a ladder-structured codesigned architecture are proposed, with the latter significantly reducing SWAP gate count through spatial qubit layout optimization.
• The digital-analog protocol uses a hybrid sequence where analog blocks are applied between digital gate operations, with the analog block duration much longer than individual gate times.
• Noise is modeled using four error channels: bit-flip, generalized damping (decoherence), dephasing, and gate infidelity via normally distributed deviations in rotation angles.
• Timing errors are modeled as normally distributed deviations in the start times of each block, simulating imperfect control over gate application instants.

Figure 1: Qubit Hamiltonian. The circles represent the qubits, each one labelled by a double index, the site in the lattice and the orientation of the spin. The arrows linking the circles represent interactions. Each chain contains $n$ qubits, the number of considered sites. The top chain holds the

Experimental results

Research questions

• RQ1 Can digital-analog quantum computation effectively simulate the 1D Fermi-Hubbard model with reduced gate count and improved fidelity?
• RQ2 How does the performance of the digital-analog approach compare to purely digital methods in terms of coherence time utilization and error resilience?
• RQ3 To what extent can a codesigned architecture minimize SWAP gate overhead in fermionic simulations?
• RQ4 How do various noise sources—decoherence, gate errors, and timing jitter—affect the simulation fidelity in realistic DAQC implementations?
• RQ5 Can symmetric Trotterization significantly reduce simulation error without increasing circuit depth or resource cost?

Key findings

• The digital-analog algorithm achieves high-fidelity simulation of the 1D Fermi-Hubbard model, with fidelity preserved even under realistic noise conditions, especially in the codesigned architecture.
• The codesigned ladder architecture reduces SWAP gate count to scale linearly with Trotter steps, independent of the number of fermions, significantly improving resource efficiency.
• Symmetric Trotterization reduces Trotter error with no additional gate cost, enabling high-precision simulation with minimal circuit depth overhead.
• Noise simulations show that the DAQC protocol maintains high performance under bit-flip, decoherence, dephasing, and gate infidelity, demonstrating robustness in NISQ devices.
• The bDAQC protocol in the codesigned architecture outperforms standard DAQC and purely digital approaches in fidelity and scalability, particularly under realistic error models.
• The results confirm that digital-analog quantum computation offers a scalable and robust alternative to purely digital quantum simulation for fermionic systems.

Figure 2: Computation of $H_{ZZ}$ . The top panel shows the graph representation of the mapping $H_{I}\rightarrow H_{ZZ}$ , given in Eq. 7b , for 3-site Fermi-Hubbard. The first graph on the left represents the Ising Hamiltonian $H_{I}$ given in Eq. ( 5 ) of the main text for the case $n_{q}=6$ . Th