[Paper Review] Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

Dietmar Fey|arXiv (Cornell University)|Dec 31, 2016

Advanced Memory and Neural Computing11 references3 citations

TL;DR

This paper evaluates hybrid MeMOS (memristor-CMOS) circuits for ternary adders, comparing them to CMOS-based ternary adders using multi-value memristor registers. It finds that while MeMOS offers advantages in static operation, CMOS adders with memristor registers outperform MeMOS in dynamic operation due to lower latency (3 ns vs. 8.5 ns) and energy (10 pJ vs. 38.8 pJ), making them preferable for high-speed applications despite higher inverter energy costs in MeMOS.

ABSTRACT

This paper investigates the potentials of using a hybrid memristor CMOS technology, called MeMOS, for the realisation of ternary adders. Ternary adders exploit the qualitative advantage of multi-value storage capability of memristors compared to conventional CMOS flip-flops storing only binary values in one cell. Furthermore they carry out an addition in $O(1)$ and are therefore considered. The MeMOS approach is compared to a CMOS solution for the ternary adders using multi value memristors as registers concerning the achievable latency and the energy consumption. It is shown that using the TEAM, VTEAM model and a model considering commercially available memristors from Known the approach of using CMOS ternary adders using memristors as multi-value register memory is to prefer. MeMOS circuits have advantages for a static operation mode, i.e. if they are operated after a reset.

Motivation & Objective

• To assess the feasibility of using MeMOS technology for implementing ternary adders with improved energy efficiency and reduced latency.
• To compare MeMOS-based ternary adders with pure CMOS solutions using multi-value memristor registers for storing ternary digits (trits).
• To evaluate the performance of ternary adders under dynamic and static operation modes using different memristor models (TEAM, VTEAM, Knowm).
• To determine whether MeMOS can outperform conventional CMOS designs in terms of energy-delay product (EDP) for scalable arithmetic computation.

Proposed method

• The study uses a C++-based simulation environment to model memristor behavior using the TEAM and VTEAM models, which describe resistance switching dynamics via differential equations.
• A hybrid MeMOS architecture integrates memristors for multi-value storage and CMOS inverters for signal regeneration and logic control.
• Ternary adders are implemented using two MeMOS-based adder designs: base_2_step_3 and base_2_step_4, with logic blocks arranged to process carry propagation in O(1) time.
• Performance is evaluated under dynamic operation (continuous data stream of 1000 operand pairs) and static operation (single reset), with varying operating frequencies and input voltages (up to 6 V).
• Energy and latency are measured across different operand widths (8, 16, 32, 64 trits), and the energy-delay product (EDP) is computed for comparison.
• Commercially available memristors from Knowm are modeled using a statistical approach to assess real-world feasibility.

Experimental results

Research questions

• RQ1 Can MeMOS-based ternary adders achieve lower energy-delay product (EDP) than CMOS adders with multi-value memristor registers?
• RQ2 How does the performance of MeMOS ternary adders vary between static and dynamic operation modes?
• RQ3 What is the impact of different memristor models (TEAM, VTEAM, Knowm) on the latency and energy consumption of MeMOS adders?
• RQ4 At what operand width does the MeMOS ternary adder begin to outperform the CMOS solution in terms of EDP?
• RQ5 How do high input voltages (e.g., 6 V) affect the reliability and performance of MeMOS adders in dynamic operation?

Key findings

• For dynamic operation, the CMOS ternary adder with memristor registers achieves a latency of 3 ns and energy consumption of 10 pJ, significantly outperforming MeMOS adders with 8.5 ns and 38.8 pJ (TEAM model).
• The MeMOS base_2_step_3 adder achieves a 60% latency improvement (1.2 ns) over the CMOS solution in static operation, but its energy-delay product (52.8 ns·pJ) is 75% worse due to unaccounted inverter energy.
• Energy consumption in MeMOS adders doubles when operand width is doubled, consistent with the regular structure and limited carry propagation.
• The base_2_step_4 MeMOS adder shows more stable behavior than base_2_step_3 in dynamic operation, despite higher latency.
• A cut-off frequency of 350 MHz is required for error-free operation of the base_2_step_3 adder, indicating timing constraints due to high voltage (6 V) and switching speed.
• The simulation results suggest that MeMOS adders are not currently superior to CMOS solutions with memristor registers for dynamic, high-speed computation, though optimization opportunities remain.