[Paper Review] Experimental Extraction and Simulation of Charge Trapping during Endurance of FeFET with TiN/HfZrO/SiO2/Si (MFIS) Gate Structure

Shujing Zhao, Fengbin Tian+9 more|arXiv (Cornell University)|Jun 30, 2021

Ferroelectric and Negative Capacitance Devices32 references5 citations

TL;DR

This study proposes an experimental method to directly extract and verify the increase in trapped charges during endurance fatigue in FeFETs with a TiN/Hf0.5Zr0.5O2/SiO2/Si (MFIS) gate structure. By measuring charges in the metal gate and Si substrate, the authors demonstrate that memory window degradation is caused by increasing electron trapping in the upper bandgap, not by ferroelectric polarization degradation or hole trapping.

ABSTRACT

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf0.5Zr0.5O2/SiO2/Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window decreases: 1) The ferroelectric characteristic of Hf0.5Zr0.5O2 is not degraded. 2) The trap density in the upper bandgap of the gate stacks increases. 3) The reason for memory window decrease is increased trapped electrons after program operation but not related to hole trapping/de-trapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.

Motivation & Objective

• To experimentally extract and quantify trapped charges during endurance fatigue in FeFETs with a TiN/HfZrO2/SiO2/Si gate stack.
• To resolve the long-standing debate on the root cause of memory window degradation in HfZrO2-based FeFETs.
• To establish a correlation between measured trapped charge and observed memory window reduction during endurance cycling.
• To model the interplay between ferroelectric polarization switching and charge trapping dynamics during endurance stress.
• To determine whether ferroelectric properties degrade or if trap density increase is the primary cause of performance loss.

Proposed method

• Employing a dual-probe method to measure charge accumulation in the TiN gate electrode and Si substrate during program/erase cycles.
• Using capacitance-voltage (C-V) measurements to extract the total trapped charge from the shift in flatband voltage and gate charge.
• Applying a physics-based simulation model to correlate experimentally extracted trapped charge with ferroelectric polarization switching behavior.
• Analyzing the evolution of trap density in the upper bandgap of the HfZrO2 layer using charge extraction data and C-V analysis.
• Comparing experimental memory window decay with simulated polarization and trap charge behavior to isolate the dominant degradation mechanism.
• Validating the model by ensuring consistency between measured charge extraction and simulated charge-trapping dynamics over multiple endurance cycles.

Experimental results

Research questions

• RQ1 What is the actual number of trapped charges accumulated during endurance cycling in TiN/Hf0.5Zr0.5O2/SiO2/Si FeFETs?
• RQ2 Does the ferroelectric polarization of Hf0.5Zr0.5O2 degrade during endurance fatigue, or is the memory window reduction due to other mechanisms?
• RQ3 Is the memory window degradation primarily caused by electron trapping or hole trapping/de-trapping in the gate stack?
• RQ4 How does the trap density in the upper bandgap of the HfZrO2 layer evolve during endurance stress?
• RQ5 Can the experimentally extracted trapped charge be consistently simulated using a physics-based model of charge-trapping and polarization switching?

Key findings

• The number of trapped charges increases significantly during endurance cycling, which is directly experimentally extracted for the first time.
• The memory window degradation is not due to degradation of the ferroelectric polarization in Hf0.5Zr0.5O2, as confirmed by consistent polarization hysteresis loops.
• The trap density in the upper bandgap of the HfZrO2 layer increases with endurance cycles, indicating trap generation or activation.
• The primary cause of memory window reduction is electron trapping after program operations, not hole trapping or de-trapping.
• The simulated data based on extracted charge and polarization behavior show excellent agreement with experimental results, validating the model.
• The study confirms that charge trapping, not ferroelectric fatigue, is the dominant degradation mechanism in this FeFET structure.