[Paper Review] Exploiting Challenges of Sub-20 nm CMOS for Affordable Technology Scaling

Kaushik Vaidyanathan|arXiv (Cornell University)|Sep 2, 2015

Advancements in Semiconductor Devices and Circuit Design4 citations

TL;DR

This paper proposes a holistic Design Technology Co-Optimization (DTCO) framework that integrates micro-architecture, circuits, layout, and process technology to enable affordable sub-20 nm CMOS scaling. By applying this approach to embedded memory, the authors achieve 25% smaller area and 50% better performance-per-watt in a parallel-access SRAM sub-block compared to traditional methods, validated via fabrication in an IBM 14SOI process.

ABSTRACT

For the past four decades, cost and features have driven CMOS scaling. Severe lithography and material limitations seen below the 20 nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of a sub-20 nm CMOS. For affordable scaling it is imperative to work past sub-20 nm technology impediments while exploiting its features. To this end, we propose to broaden the scope of design technology co-optimization (DTCO) to be more holistic by including micro-architecture design and CAD, along with circuits, layout and process technology. Applying such holistic DTCO to the most significant block in a system-on-chip (SoC), embedded memory, we can synthesize smarter and efficient embedded memory blocks that are customized to application needs. To evaluate the efficacy of the proposed holistic DTCO process, we designed, fabricated and tested several design experiments in a state-of-the-art IBM 14SOI process. DTCOed leaf cells, standard cells and SRAM bitcells were robust during testing, but failed to meet node to node area scaling requirements. Holistic DTCO, when applied to a widely used parallel access SRAM sub-block, consumed 25% less area with a 50% better performance per watt compared to a traditional implementation using compiled SRAM blocks and standard cells. To extend the benefits of holistic DTCO to other embedded memory intensive sub-blocks in SoCs, we developed a readily customizable smart memory synthesis framework (SMSF). We believe that such an approach is important to establish an affordable path for sub-20 nm scaling.

Motivation & Objective

• To address the growing challenge of affordable CMOS scaling below the 20 nm node due to severe lithography and material limitations.
• To overcome the limitations of traditional DTCO by expanding its scope to include micro-architecture and CAD alongside circuits, layout, and process.
• To develop a customizable smart memory synthesis framework (SMSF) that extends benefits of holistic DTCO to embedded memory-intensive sub-blocks in SoCs.
• To demonstrate the efficacy of holistic DTCO through physical implementation and testing in a state-of-the-art 14SOI process.
• To establish a sustainable, cost-effective path for sub-20 nm technology scaling beyond conventional co-optimization.

Proposed method

• Extends DTCO beyond circuit and layout co-optimization to include micro-architecture and CAD components for a more holistic design approach.
• Applies holistic DTCO to embedded memory blocks, particularly a parallel-access SRAM sub-block, to tailor designs to application-specific needs.
• Designs, fabricates, and tests DTCO-optimized leaf cells, standard cells, and SRAM bitcells in an IBM 14SOI process to validate robustness.
• Develops a smart memory synthesis framework (SMSF) that enables rapid customization of embedded memory sub-blocks for diverse SoC workloads.
• Uses physical implementation and benchmarking to compare holistic DTCO designs against traditional implementations using compiled SRAM blocks and standard cells.
• Employs area and performance-per-watt metrics to evaluate and quantify improvements in scaling efficiency.

Experimental results

Research questions

• RQ1 Can a holistic DTCO framework that includes micro-architecture and CAD significantly improve scaling efficiency below 20 nm?
• RQ2 To what extent can holistic DTCO reduce area and improve energy efficiency in embedded memory sub-blocks?
• RQ3 How does the performance of DTCO-optimized SRAM sub-blocks compare to traditional implementations using standard cell libraries?
• RQ4 Can a customizable smart memory synthesis framework (SMSF) be effectively used to scale embedded memory blocks across diverse SoC applications?
• RQ5 Is there a viable, affordable path for sub-20 nm CMOS scaling when traditional co-optimization fails?

Key findings

• Holistic DTCO reduced the area of a parallel-access SRAM sub-block by 25% compared to a traditional implementation using compiled SRAM blocks and standard cells.
• The DTCO-optimized SRAM sub-block achieved 50% better performance-per-watt than the traditional implementation.
• DTCO-optimized leaf cells, standard cells, and SRAM bitcells were robust during physical testing in the IBM 14SOI process.
• The proposed smart memory synthesis framework (SMSF) enables rapid, customizable deployment of optimized embedded memory sub-blocks across diverse SoC designs.
• Traditional DTCO approaches failed to meet node-to-node area scaling requirements, highlighting the need for a broader co-optimization strategy.
• The results validate that holistic DTCO offers a viable, affordable path for sub-20 nm CMOS scaling beyond the limitations of conventional co-optimization.