[Paper Review] GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Lilas Alrahis, Johann Knechtel+3 more|arXiv (Cornell University)|Aug 4, 2022

Semiconductor materials and devices4 citations

TL;DR

GNN4REL proposes a graph neural network framework that predicts circuit reliability degradation due to process variation and device aging without requiring access to standard-cell libraries, transistor models, or static timing analysis. Trained on a 14nm FinFET technology model, it achieves sub-0.01% mean absolute error in delay degradation estimation within seconds per path.

ABSTRACT

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated for advanced technology nodes, where transistor dimensions reach atomic levels and established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static timing analysis (STA) equips designers with accurate statistical delay distributions. Timing guardbands that are small, yet sufficient, can then be effectively estimated. However, such analysis is costly as it requires intensive Monte-Carlo simulations. Further, it necessitates access to confidential physics-based aging models to generate the standard-cell libraries required for STA. In this work, we employ graph neural networks (GNNs) to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit. Our proposed GNN4REL framework empowers designers to perform rapid and accurate reliability estimations without accessing transistor models, standard-cell libraries, or even STA; these components are all incorporated into the GNN model via training by the foundry. Specifically, GNN4REL is trained on a FinFET technology model that is calibrated against industrial 14nm measurement data. Through our extensive experiments on EPFL and ITC-99 benchmarks, as well as RISC-V processors, we successfully estimate delay degradations of all paths -- notably within seconds -- with a mean absolute error down to 0.01 percentage points.

Motivation & Objective

• To address the challenge of accurate, efficient reliability estimation in advanced technology nodes where process variation and device aging severely impact circuit timing.
• To eliminate the need for designers to access proprietary standard-cell libraries or perform costly Monte-Carlo simulations.
• To enable fast and precise prediction of delay degradation due to process variation and aging using a single, trained GNN model.
• To protect foundry-proprietary information by embedding physics-based aging and variation models into the GNN during training.
• To provide a scalable, generic solution for pre-silicon reliability assessment applicable across diverse circuit designs.

Proposed method

• GNN4REL employs a graph neural network (GNN) to model the circuit netlist as a heterogeneous graph, capturing transistor-level and path-level dependencies.
• The GNN is trained on a 14nm FinFET technology model calibrated against industrial 14nm measurement data, incorporating process variation and aging effects.
• Input features include gate-level netlist structure, transistor types, and timing-related attributes such as switching transition and load capacitance.
• The model predicts statistical measures (mean, standard deviation, maximum) of delay degradation for any path in the circuit.
• Training is performed once per technology node, with inference taking only seconds per design, bypassing traditional STA and simulation.
• The framework is trained end-to-end on 1,000 timing paths per design, using self-referencing and cross-validation scenarios to ensure generalization.

Experimental results

Research questions

• RQ1 Can a GNN-based model accurately predict delay degradation due to process variation and device aging without requiring access to standard-cell libraries or STA?
• RQ2 How does the performance of GNN4REL compare to conventional Monte-Carlo and statistical STA methods in terms of accuracy and speed?
• RQ3 Can GNN4REL generalize across different circuit benchmarks and RISC-V processor designs with minimal retraining?
• RQ4 What is the impact of varying training data splits (e.g., self-referencing vs. cross-validation) on model accuracy and robustness?
• RQ5 To what extent can GNN4REL reduce the computational overhead of reliability estimation compared to traditional methods?

Key findings

• GNN4REL achieves a mean absolute error of just 0.01 percentage points in predicting delay degradation across all tested paths.
• Reliability estimation is completed in a few seconds per design, significantly outpacing traditional Monte-Carlo simulations that take up to 2.2 hours per design.
• The model generalizes effectively across diverse benchmarks, including ITC-99, EPFL, and RISC-V processors, under both self-referencing and cross-validation scenarios.
• Training time for GNN4REL is approximately 2 hours per benchmark, a one-time cost that enables rapid inference on any new design.
• The framework eliminates the need for STA, circuit simulations, and access to proprietary transistor models during inference, enhancing privacy and efficiency.
• GNN4REL outperforms existing ML-based methods like Aadam and ML-based cell-lib characterization by avoiding per-cell training, simulation dependency, and STA invocation.