[Paper Review] Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors

Sergi Abadal, Robert Guirado+19 more|arXiv (Cornell University)|Nov 8, 2020

Interconnection Networks and Systems19 references4 citations

TL;DR

This paper proposes graphene-based terahertz wireless interconnects as a scalable, reconfigurable solution for massive heterogeneous multi-chip processors, leveraging graphene's unique beam and frequency agility to overcome wired interconnect bottlenecks. The key contribution is a vision for agile, high-bandwidth, low-latency wireless networks within packages that adapt dynamically to diverse communication demands in AI and accelerator workloads.

ABSTRACT

The main design principles in computer architecture have recently shifted from a monolithic scaling-driven approach to the development of heterogeneous architectures that tightly co-integrate multiple specialized processor and memory chiplets. In such data-hungry multi-chip architectures, current Networks-in-Package (NiPs) may not be enough to cater to their heterogeneous and fast-changing communication demands. This position paper makes the case for wireless in-package nanonetworking as the enabler of efficient and versatile wired-wireless interconnect fabrics for massive heterogeneous processors. To that end, the use of graphene-based antennas and transceivers with unique frequency-beam reconfigurability in the terahertz band is proposed. The feasibility of such a nanonetworking vision and the main research challenges towards its realization are analyzed from the technological, communications, and computer architecture perspectives.

Motivation & Objective

• Address the growing communication bottleneck in massive heterogeneous multi-chip processors due to increasing data demands and limitations of wired interconnects.
• Overcome the inflexibility and scalability issues of existing Network-in-Package (NiP) and Network-on-Chip (NoC) architectures in multi-chip systems.
• Explore the feasibility of using graphene-based terahertz transceivers and antennas to enable reconfigurable, high-throughput wireless interconnects within chip packages.
• Enable dynamic, adaptive communication fabrics that support diverse workloads, including data-intensive AI accelerators and multicasting patterns.
• Identify and address cross-layer challenges in integrating wireless interconnects into computer architecture, from physical layer to system-level simulation.

Proposed method

• Propose the use of graphene-based antennas and transceivers operating in the terahertz band (0.3–3 THz) for high-bandwidth, low-energy wireless interconnects within multi-chip packages.
• Leverage graphene’s unique electrical and optical properties to enable frequency-beam reconfigurability, allowing dynamic adaptation to changing communication patterns.
• Integrate wireless interconnects as a complementary fabric to wired NoCs/NiPs, particularly for off-chip and high-latency communication scenarios.
• Develop a co-design methodology that links physical-layer capabilities (beamforming, frequency agility) with MAC layer protocols and system architecture.
• Introduce the need for new system simulators that model wireless behavior at scale, incorporating thermal, interference, and propagation effects without relying on full physical-layer simulations.
• Model wireless performance using behavioral models derived from antenna characterization, wave propagation, and circuit design, enabling efficient architectural exploration.

Experimental results

Research questions

• RQ1 Can graphene-based terahertz wireless interconnects provide sufficient bandwidth and reconfigurability to meet the dynamic communication demands of massive heterogeneous multi-chip processors?
• RQ2 How can frequency-beam reconfigurability in graphene transceivers enable efficient support for one-to-many and broadcast communication patterns common in AI accelerators?
• RQ3 What are the key architectural and system-level challenges in integrating wireless interconnects into existing NiP and NoC-based multi-chip systems?
• RQ4 How can system simulators be enhanced to model wireless interconnects accurately at the architectural level, including interference, thermal impact, and protocol behavior?
• RQ5 What co-design methodologies are required to optimize the integration of wireless interconnects with application workloads such as deep neural networks?

Key findings

• Graphene-based terahertz transceivers offer high bandwidth and beam-frequency reconfigurability, enabling agile, dynamic interconnects that adapt to varying communication demands.
• Wireless interconnects can alleviate the latency and energy bottlenecks of wired NoCs and NiPs, especially for long-distance and broadcast communications in multi-chip systems.
• The integration of wireless interconnects is particularly beneficial for data-intensive workloads such as AI accelerators, where frequent multicasting and long-range data transfers are common.
• Existing computer architecture simulators lack adequate support for wireless communication modeling, necessitating new simulation frameworks that integrate physical-layer behavior with system-level performance.
• Key challenges remain in the integration of graphene antennas into chip environments, protocol-architecture co-design, and accurate modeling of interference and thermal effects in wireless-enabled systems.
• The proposed wireless vision enables a shift from rigid, wired interconnect fabrics to flexible, reconfigurable nanonetworks capable of supporting future heterogeneous and scalable processor architectures.