[Paper Review] Low charge noise quantum dots with industrial CMOS manufacturing

Asser Elsayed, Mohamed Shehata+13 more|arXiv (Cornell University)|Dec 13, 2022

Quantum and electron transport phenomena61 references4 citations

TL;DR

This paper demonstrates low charge noise silicon MOS spin qubits fabricated using a customized 300mm industrial CMOS process line, achieving a record-low average charge noise of 0.61 μeV/√Hz at 1 Hz and below 0.1 μeV/√Hz in select devices. By optimizing the MOS gate stack and leveraging CMOS scalability, the authors achieve stable, uniform quantum dot operation at milli-Kelvin temperatures with noise well described by a two-level fluctuator model.

ABSTRACT

Silicon spin qubits are among the most promising candidates for large scale quantum computers, due to their excellent coherence and compatibility with CMOS technology for upscaling. Advanced industrial CMOS process flows allow wafer-scale uniformity and high device yield, but off the shelf transistor processes cannot be directly transferred to qubit structures due to the different designs and operation conditions. To therefore leverage the know-how of the micro-electronics industry, we customize a 300mm wafer fabrication line for silicon MOS qubit integration. With careful optimization and engineering of the MOS gate stack, we report stable and uniform quantum dot operation at the Si/SiOx interface at milli-Kelvin temperature. We extract the charge noise in different devices and under various operation conditions, demonstrating a record-low average noise level of 0.61 $μ$eV/${\sqrt{Hz}}$ at 1 Hz and even below 0.1 $μ$eV/${\sqrt{Hz}}$ for some devices and operating conditions. By statistical analysis of the charge noise with different operation and device parameters, we show that the noise source can indeed be well described by a two-level fluctuator model. This reproducible low noise level, in combination with uniform operation of our quantum dots, marks CMOS manufactured MOS spin qubits as a mature and highly scalable platform for high fidelity qubits.

Motivation & Objective

• To integrate silicon MOS spin qubits using a 300mm industrial CMOS fabrication line for scalable quantum computing.
• To achieve low charge noise levels essential for high-fidelity qubit operation in silicon-based quantum systems.
• To demonstrate uniform and stable quantum dot operation at milli-Kelvin temperatures using CMOS-compatible processes.
• To identify and characterize the dominant charge noise sources in CMOS-fabricated quantum dots.
• To validate the two-level fluctuator model as the dominant noise mechanism through statistical analysis.

Proposed method

• Customization of a 300mm industrial CMOS process flow for silicon MOS qubit integration, focusing on gate stack engineering.
• Fabrication of quantum dots at the Si/SiOx interface using standard CMOS lithography and etching techniques.
• Low-temperature electrical measurements at milli-Kelvin temperatures to assess quantum dot stability and charge noise.
• Charge noise spectroscopy across multiple devices and operation conditions to extract noise power spectral density.
• Statistical analysis of noise data to test the two-level fluctuator model and correlate noise with device parameters.
• Use of a 300mm wafer-scale platform to ensure uniformity and high yield across devices.

Experimental results

Research questions

• RQ1 Can silicon MOS spin qubits be successfully fabricated using a customized industrial CMOS process line?
• RQ2 What is the achievable charge noise level in CMOS-fabricated silicon quantum dots at milli-Kelvin temperatures?
• RQ3 How does the charge noise vary across different devices and operation conditions in the CMOS platform?
• RQ4 Is the two-level fluctuator model a valid description of the dominant charge noise source in these devices?
• RQ5 To what extent can CMOS manufacturing enable uniform, scalable, and low-noise quantum dot operation?

Key findings

• The authors achieved a record-low average charge noise of 0.61 μeV/√Hz at 1 Hz across multiple devices.
• In select devices and operating conditions, charge noise dropped below 0.1 μeV/√Hz, indicating exceptional noise suppression.
• Statistical analysis confirmed that the dominant charge noise source is well described by a two-level fluctuator model.
• Stable and uniform quantum dot operation was demonstrated across a 300mm wafer, enabling wafer-scale scalability.
• The MOS gate stack engineering significantly reduced interface and oxide defects, contributing to low noise performance.
• The results establish CMOS-manufactured silicon MOS qubits as a mature and scalable platform for high-fidelity quantum computing.