[Paper Review] MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning

Yao Lai, Yao Mu+1 more|arXiv (Cornell University)|Nov 24, 2022

Advanced Memory and Neural Computing21 citations

TL;DR

MaskPlace reframes chip placement as pixel-level visual representation learning and uses an RL policy with dense rewards to place macros on a 224x224 canvas, achieving valid 0% overlap layouts and substantial wirelength reductions compared with prior methods.

ABSTRACT

Placement is an essential task in modern chip design, aiming at placing millions of circuit modules on a 2D chip canvas. Unlike the human-centric solution, which requires months of intense effort by hardware engineers to produce a layout to minimize delay and energy consumption, deep reinforcement learning has become an emerging autonomous tool. However, the learning-centric method is still in its early stage, impeded by a massive design space of size ten to the order of a few thousand. This work presents MaskPlace to automatically generate a valid chip layout design within a few hours, whose performance can be superior or comparable to recent advanced approaches. It has several appealing benefits that prior arts do not have. Firstly, MaskPlace recasts placement as a problem of learning pixel-level visual representation to comprehensively describe millions of modules on a chip, enabling placement in a high-resolution canvas and a large action space. It outperforms recent methods that represent a chip as a hypergraph. Secondly, it enables training the policy network by an intuitive reward function with dense reward, rather than a complicated reward function with sparse reward from previous methods. Thirdly, extensive experiments on many public benchmarks show that MaskPlace outperforms existing RL approaches in all key performance metrics, including wirelength, congestion, and density. For example, it achieves 60%-90% wirelength reduction and guarantees zero overlaps. We believe MaskPlace can improve AI-assisted chip layout design. The deliverables are released at https://laiyao1.github.io/maskplace.

Motivation & Objective

• Motivate automated chip placement to handle millions of modules with high efficiency and valid layouts.
• Introduce a pixel-level visual representation to encode net and pin configurations on a large canvas.
• Develop a reinforcement learning policy that produces dense rewards to optimize wirelength while ensuring non-overlap.
• Enable full-canvas placement (224x224) with a large action space and efficient computation.
• Demonstrate superiority over prior optimization-based and learning-based placement methods across public benchmarks.

Proposed method

• Represent placement as a Markov Decision Process with one module placed per step.
• Use three pixel-level masks (position, wire, view) to encode state and enable learning without losing pin-level information.
• Fuse masks via 1x1 convolutions in a policy network to predict a dense action probability map over the canvas.
• Define a dense reward based on partial HPWL reduction per step to guide learning without sparse rewards.
• Incorporate a congestion satisfaction block to enforce hard congestion constraints during action selection.
• Train with PPO2 actor-critic framework using HPWL as the main reward and a congestion-aware final action selection step.

Experimental results

Research questions

• RQ1 Can a pixel-level visual representation of chip nets and pins support high-quality, non-overlapping macro placement on a large canvas?
• RQ2 Does a dense HPWL-based reward in an RL framework outperform sparse-reward or hypergraph-based representations for chip placement?
• RQ3 How does MaskPlace compare to state-of-the-art optimization- and learning-based placers across standard benchmarks in wirelength, density, and congestion?
• RQ4 Is it feasible to place macros on a full 224x224 canvas with zero overlaps and competitive routing metrics within reasonable compute time?

Key findings

• MaskPlace consistently achieves 0% overlap across evaluated benchmarks.
• MaskPlace yields substantial wirelength reductions compared with Graph Placement and DeepPR (e.g., up to 60%-90% in some comparisons).
• On 24 public benchmarks, MaskPlace outperforms recent RL and optimization-based methods in wirelength, congestion, and density metrics.
• When compared to Graph Placement, MaskPlace shows large HPWL improvements and zero overlaps in most ISPD benchmarks.
• MaskPlace operates on a full 224x224 canvas with a high-resolution representation and demonstrates faster inference than several competing learning-based methods.
• A congestion-satisfaction mechanism ensures hard density constraints are met while maintaining efficient optimization of wirelength.