[Paper Review] Multi-Bit Read and Write Methodologies for Diode-STTRAM Crossbar Array

Mohammad Nasim Imtiaz Khan, Swaroop Ghosh+2 more|arXiv (Cornell University)|Jun 1, 2016

Advanced Memory and Neural Computing7 references3 citations

TL;DR

This paper proposes multi-bit read and write techniques for diode-STTRAM crossbar arrays to overcome bandwidth limitations in emerging non-volatile memory crossbars. By adjusting half-selected cell biasing—700 mV for read and 50 mV pulses for write—it enables 512-bit reads and 2-bit writes while preserving 512×512 array retention for 2.04 years, significantly improving efficiency and scalability without disturbing unintended cells.

ABSTRACT

Crossbar arrays using emerging non-volatile memory technologies such as Resistive RAM (ReRAM) offer high density, fast access speed and low-power. However the bandwidth of the crossbar is limited to single-bit read/write per access to avoid selection of undesirable bits. We propose a technique to perform multi-bit read and write in a diode-STTRAM (Spin Transfer Torque RAM) crossbar array. Simulation shows that the biasing voltage of half-selected cells can be adjusted to improve the sense margin during read and thus reduce the sneak path through the half-selected cells. In write operation, the half-selected cells are biased with a pulse voltage source which increases the write latency of these cells and enables to write 2-bits while keeping the half-selected bits undisturbed. Simulation results indicate biasing the half-selected cells by 700mV can enable reading as much as 512-bits while sustaining 512x512 crossbar with 2.04 years retention. The 2-bit writing requires pulsing by 50mV to optimize energy.

Motivation & Objective

• To overcome the single-bit bandwidth limitation in crossbar arrays using emerging non-volatile memories like STTRAM.
• To enable multi-bit operations without disturbing half-selected cells during read and write.
• To improve sense margin during read and reduce sneak path interference in crossbar arrays.
• To maintain long-term data retention (2.04 years) in a 512×512 crossbar array under multi-bit operation.
• To optimize energy efficiency in write operations through pulsed voltage biasing.

Proposed method

• Adjusts the bias voltage of half-selected cells to 700 mV during read operations to improve sense margin and suppress sneak path currents.
• Applies a pulsed voltage source to half-selected cells during write operations to increase write latency and ensure reliable 2-bit writing.
• Uses diode-based crossbar architecture to isolate unintended cells and reduce cross-talk during multi-bit operations.
• Employs voltage-level tuning to balance read reliability and write disturbance, maintaining data integrity.
• Simulates the crossbar array under various biasing conditions to evaluate performance and retention.
• Validates the approach using simulation-based analysis of sense margin, write latency, and retention time.

Experimental results

Research questions

• RQ1 Can multi-bit read operations be reliably performed in a diode-STTRAM crossbar array without increasing error rates?
• RQ2 How can the sense margin be improved during read operations to suppress sneak path currents in half-selected cells?
• RQ3 What voltage biasing strategy enables 2-bit write operations while preserving data in half-selected cells?
• RQ4 What is the maximum number of bits that can be read simultaneously while maintaining 2.04-year retention in a 512×512 array?
• RQ5 How can write energy be minimized while ensuring reliable multi-bit writing?

Key findings

• Applying a 700 mV bias to half-selected cells enables reliable reading of up to 512 bits in a 512×512 diode-STTRAM crossbar array.
• The proposed read methodology maintains a sense margin sufficient to sustain 2.04 years of data retention in the crossbar array.
• A 50 mV pulsed voltage source applied to half-selected cells during write operations enables 2-bit writing with optimized energy efficiency.
• The technique successfully prevents unintended write disturbances in half-selected cells during multi-bit write operations.
• Simulation results confirm that the method maintains high reliability and scalability for large crossbar arrays.
• The approach achieves a significant improvement in bandwidth efficiency without compromising retention or data integrity.