[Paper Review] On Resistive Memories: One Step Row Readout Technique and Sensing Circuitry

Mohammed E. Fouda, Ahmed M. Eltawil+1 more|arXiv (Cornell University)|Mar 4, 2019

Advanced Memory and Neural Computing17 references4 citations

TL;DR

This paper proposes a one-step row readout technique for selector-less resistive crossbar arrays that eliminates sneak path currents by biasing all rows except the active one to a reference voltage, enabling parallel reading of entire rows in a single cycle. The method achieves high throughput with minimal circuit overhead and supports 3D stacking, outperforming prior techniques in array utilization and speed despite higher power consumption.

ABSTRACT

Transistor-based memories are rapidly approaching their maximum density per unit area. Resistive crossbar arrays enable denser memory due to the small size of switching devices. However, due to the resistive nature of these memories, they suffer from current sneak paths complicating the readout procedure. In this paper, we propose a row readout technique with circuitry that can be used to read {selector-less} resistive crossbar based memories. High throughput reading and writing techniques are needed to overcome the memory-wall bottleneck problem and to enable near memory computing paradigm. The proposed technique can read the entire row of dense crossbar arrays in one cycle, unlike previously published techniques. The requirements for the readout circuitry are discussed and satisfied in the proposed circuit. Additionally, an approximated expression for the power consumed while reading the array is derived. A figure of merit is defined and used to compare the proposed approach with existing reading techniques. Finally, a quantitative analysis of the effect of biasing mismatch on the array size is discussed.

Motivation & Objective

• Address the sneak path problem in high-density, selector-less resistive crossbar arrays that hinder reliable data reading.
• Enable high-throughput, parallel row reading to overcome the memory wall bottleneck in near-memory computing.
• Design a sensing circuit that supports full-row readout without requiring reference bits or multiple cycles.
• Analyze the impact of biasing mismatch on array size and power consumption for robust operation.
• Evaluate compatibility with 3D stacking and multilevel resistive memory architectures for future scalability.

Proposed method

• Apply a reference bias voltage $V_B$ to all input and output ports except the active row, which is driven with $V_{DD}$, to eliminate current flow through non-selected rows.
• Sense the output current from each bitline in the active row, which is proportional to the resistance of the selected cell (LRS or HRS), thereby distinguishing states without sneak path interference.
• Use a current-sensing circuit with a comparator to detect the current level, where input voltage to the comparator is limited by noise margin (e.g., 10 mV) to ensure reliable decision-making.
• Derive an approximated power model for reading, with total power consumption expressed as $P riangleq V_{DD} imes I_{total}$, where $I_{total}$ includes both desired and unwanted currents.
• Define a figure of merit (FOM) combining power, array utilization, effective array size, and throughput to quantitatively compare the proposed method with prior techniques.
• Analyze the maximum allowable column width $N$ under bias mismatch by modeling unwanted current $I_{unW}$ as a function of voltage mismatch $ riangle V$, device resistance, and number of columns.

Experimental results

Research questions

• RQ1 Can a one-cycle, full-row readout technique be designed for selector-less resistive crossbars that eliminates sneak path interference?
• RQ2 How does the proposed sensing circuitry enable high-throughput reading without requiring reference cells or multiple cycles?
• RQ3 What is the maximum array size that can be reliably read under voltage mismatch, and how does it scale with device nonlinearity?
• RQ4 How does the power consumption of the proposed technique compare to existing methods, and what trade-offs exist in terms of performance and efficiency?
• RQ5 To what extent is the proposed technique compatible with 3D stacking and multilevel resistive memory architectures?

Key findings

• The proposed technique enables full-row parallel readout in a single cycle, achieving maximum throughput and 100% array utilization, unlike prior methods requiring multiple cycles or reference bits.
• For linear devices with 2 mV bias mismatch, the maximum column width $N$ is limited to 195 to maintain a 10 mV noise margin in the comparator.
• For nonlinear switching devices, the maximum column width increases significantly to approximately 6,500 under the same 2 mV mismatch due to reduced sensitivity of unwanted currents to voltage mismatch.
• The proposed method consumes 4.7× more power than the technique in [8], but achieves over 100× better figure of merit (FOM) due to superior throughput and array utilization.
• The technique is compatible with 3D stacking, where multiple layers share the same readout circuitry via a level decoder, enabling scalable, high-density memory architectures.
• The method supports multilevel memory operation, especially with nonlinear devices, though sensing circuitry would require modification to distinguish multiple resistance states.