[Paper Review] Reversible Fault-Tolerant Logic

P. Oscar Boykin, Vwani Roychowdhury|ArXiv.org|Apr 4, 2005

Distributed systems and fault tolerance10 citations

TL;DR

This paper presents a fault-tolerant design for reversible logic circuits using reversible majority multiplexing to achieve reliable computation despite high gate error rates (up to 1/108). It establishes error thresholds of 1/273 in 2D and 23% lower in 1D lattices, while quantifying entropy dissipation and showing that entropic advantages of reversible computing are lost when error rates approach the threshold, requiring O(log 1/g) levels of error correction for energy efficiency.

ABSTRACT

It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiting factor. Reversible computing can potentially require arbitrarily small amounts of energy. Recently several nano-scale devices which have the potential to scale, and which naturally perform reversible logic, have emerged. This paper addresses several fundamental issues that need to be addressed before any nano-scale reversible computing systems can be realized, including reliability and performance trade-offs and architecture optimization. Many nano-scale devices will be limited to only near neighbor interactions, requiring careful optimization of circuits. We provide efficient fault-tolerant (FT) circuits when restricted to both 2D and 1D. Finally, we compute bounds on the entropy (and hence, heat) generated by our FT circuits and provide quantitative estimates on how large can we make our circuits before we lose any advantage over irreversible computing.

Motivation & Objective

• To address reliability and performance trade-offs in nano-scale reversible computing systems with inherently unreliable gates.
• To optimize fault-tolerant (FT) circuit design under local connectivity constraints, such as 1D and 2D lattices with only nearest-neighbor interactions.
• To compute entropy bounds and quantify heat dissipation in FT reversible circuits, determining when the energy advantage of reversibility is lost.
• To provide a scalable, gate-level fault-tolerant framework for reversible classical computing that is applicable to emerging nano-devices and quantum-classical hybrid systems.

Proposed method

• Uses a reversible majority (MAJ) gate-based multiplexing scheme instead of irreversible NAND gates to enable fault tolerance in reversible logic.
• Applies a hierarchical error-recovery mechanism with ancillary bits to detect and correct errors at each level of computation.
• Models gate errors as independent failures with probability g, where a faulty gate outputs uniformly random 3-bit states with probability g.
• Derives entropy bounds using subadditivity: upper bound H_L ≤ Ḡ^L κ√g and lower bound H_L ≥ (3E)^{L-1}g, where E is the number of gates in recovery.
• Computes overhead in gate count and circuit depth, showing O(T log^4.75 T) gate complexity for T logical gates to achieve constant error rate independent of T.
• Analyzes local connectivity by restricting circuits to 1D and 2D lattices, computing reduced error thresholds under these constraints.

Experimental results

Research questions

• RQ1 What is the maximum error rate per gate (g) for which fault-tolerant reversible circuits can still achieve reliable computation?
• RQ2 How does local connectivity (1D vs. 2D) affect the error threshold in reversible fault-tolerant circuits?
• RQ3 To what extent is the entropy reduction benefit of reversible computing compromised by error correction overhead?
• RQ4 What is the minimum number of error correction levels required to preserve the energy efficiency of reversible computing under realistic error rates?
• RQ5 Can a fault-tolerant reversible circuit be constructed with only nearest-neighbor interactions, and what is the performance penalty?

Key findings

• The fault-tolerant reversible circuit design supports gate error rates up to 1/108 while maintaining a constant module error rate independent of circuit size.
• In 2D lattices with only nearest-neighbor connections, the error threshold is 1/273, significantly higher than in non-local models.
• A 1D lattice with 27 bits width but arbitrary length has an error threshold only 23% lower than the full 2D case, demonstrating strong scalability under locality constraints.
• Entropy dissipation in the error-recovery process grows exponentially with depth L, and the entropic advantage of reversible computing is lost when g approaches the threshold, even for small g.
• The circuit requires O(log(1/g)) levels of error correction to preserve energy efficiency, with overhead scaling as O(T log^4.75 T) in gate count for T logical gates.
• The lower bound on entropy per gate is g(3E)^{L-1}, and the upper bound is Ḡ^L κ√g, showing that entropy grows exponentially with depth unless g is sufficiently small.