[Paper Review] Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Mostafizur Rahman, Santosh Khasanvis+3 more|arXiv (Cornell University)|Apr 2, 2014

Semiconductor materials and devices31 references19 citations

TL;DR

Skybridge proposes a 3D integrated circuit technology as a scalable alternative to CMOS, using a uniform 3D fabric template with vertical interconnects and thermal management to overcome scaling limits. Simulations show 30–60× higher density, 3.5× better performance per watt, and 10× shorter interconnects than 16-nm CMOS, enabling continued IC scaling beyond CMOS limits.

ABSTRACT

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.

Motivation & Objective

• To address the fundamental scaling limits of CMOS at sub-20nm nodes, particularly the interconnection bottleneck and device physics constraints.
• To overcome the incompatibility of traditional CMOS manufacturing and customization with 3D IC architectures.
• To enable continuous IC scaling beyond CMOS by developing a co-designed 3D fabric-centric technology platform.
• To achieve significant improvements in density, power efficiency, and interconnect length through a unified 3D template and vertical integration.

Proposed method

• Designing a 3D IC fabric using a uniform 3D template that integrates device, circuit, connectivity, thermal management, and manufacturing processes co-designedly.
• Implementing vertical interconnects and through-silicon vias (TSVs) to enable high-density, low-latency 3D interconnects across stacked layers.
• Employing a bottom-up simulation framework that models detailed material systems, process flows, device characteristics, and circuit parasitics.
• Integrating fabric-level heat extraction features such as thermal vias and optimized layer stacking to manage thermal profiles in 3D ICs.
• Validating the design with multiple test cases, including a full microprocessor implementation, across various process and design parameters.
• Using a co-architectural approach to align device-level design with circuit style, interconnect topology, and thermal constraints in a 3D context.

Experimental results

Research questions

• RQ1 Can a 3D IC technology be co-designed from device to system level to overcome CMOS scaling limits?
• RQ2 How can vertical integration in 3D ICs be made manufacturable and scalable beyond current die-stacking limitations?
• RQ3 What performance, power, and area benefits can be achieved with a 3D fabric-centric design compared to scaled CMOS?
• RQ4 How effectively can thermal management be embedded in a 3D IC fabric to prevent hotspots and ensure reliability?
• RQ5 To what extent can interconnect length and delay be reduced in 3D ICs using a uniform 3D template and optimized via distribution?

Key findings

• Skybridge achieves 30–60× higher integration density compared to 16-nm CMOS, due to vertical stacking and optimized interconnects.
• Performance per watt improves by a factor of 3.5× over scaled 16-nm CMOS, indicating significant energy efficiency gains.
• Interconnect lengths are reduced by a factor of 10× compared to 16-nm CMOS, directly addressing the interconnection bottleneck.
• Thermal simulations confirm that fabric-level heat extraction features effectively manage temperature profiles in 3D ICs, preventing hotspots.
• Bottom-up simulations of a full microprocessor design validate the scalability and performance benefits of the Skybridge architecture.
• The co-designed 3D fabric enables continuous scaling beyond CMOS, offering a viable path for 21st-century IC development.