[Paper Review] Special Session: Reliability Analysis for ML/AI Hardware

Shamik Kundu, Kanad Basu+5 more|arXiv (Cornell University)|Mar 22, 2021

Advanced Memory and Neural Computing79 references4 citations

TL;DR

This paper investigates reliability challenges in ML/AI hardware, focusing on DRAM faults in DNN accelerators and circuit aging/endurance in neuromorphic systems. It proposes system-level mitigation techniques—RENEU for reducing circuit aging in spiking neural networks and eSpine for improving PCM endurance via intelligent workload mapping—achieving 38% lower aging and extended lifetime in neuromorphic hardware.

ABSTRACT

Artificial intelligence (AI) and Machine Learning (ML) are becoming pervasive in today's applications, such as autonomous vehicles, healthcare, aerospace, cybersecurity, and many critical applications. Ensuring the reliability and robustness of the underlying AI/ML hardware becomes our paramount importance. In this paper, we explore and evaluate the reliability of different AI/ML hardware. The first section outlines the reliability issues in a commercial systolic array-based ML accelerator in the presence of faults engendering from device-level non-idealities in the DRAM. Next, we quantified the impact of circuit-level faults in the MSB and LSB logic cones of the Multiply and Accumulate (MAC) block of the AI accelerator on the AI/ML accuracy. Finally, we present two key reliability issues -- circuit aging and endurance in emerging neuromorphic hardware platforms and present our system-level approach to mitigate them.

Motivation & Objective

• To analyze the impact of DRAM bit-level faults on DNN accelerator accuracy due to device-level non-idealities and variable retention times.
• To evaluate the sensitivity of MAC units in DNN accelerators to circuit faults in MSB and LSB logic cones, identifying critical fault regions.
• To address circuit aging and endurance limitations in emerging neuromorphic hardware using PCM-based crossbars.
• To develop system-level techniques that co-optimize workload mapping with hardware reliability constraints for improved longevity and accuracy.

Proposed method

• Injected bit-wise faults into DRAM memory subsystems of a DNN accelerator to characterize accuracy degradation across multiple quantized DNN models.
• Performed exhaustive fault characterization on multivariate datasets to assess the impact of DRAM retention time and refresh rate on inference accuracy.
• Analyzed MAC circuit faults by isolating MSB and LSB logic cones, determining fault tolerance thresholds for acceptable accuracy degradation.
• Proposed RENEU, a system-level mapping technique that minimizes circuit aging in neuromorphic hardware by optimizing neuron and synapse placement based on aging models.
• Developed eSpine, a two-step framework using Kernighan-Lin graph partitioning and particle swarm optimization (PSO) to map workloads to PCM crossbars with variable endurance.
• Integrated technology-aware models of parasitic voltage drops and self-heating in PCM crossbars to guide placement decisions for improved endurance.

Experimental results

Research questions

• RQ1 How do DRAM bit-flip faults caused by variable retention times affect the inference accuracy of quantized DNNs in edge accelerators?
• RQ2 What is the sensitivity of MAC units to circuit-level faults in the MSB and LSB logic cones, and what fault rates are tolerable without exceeding accuracy degradation thresholds?
• RQ3 How does self-heating asymmetry due to parasitic voltage drops in PCM crossbars affect the endurance of synaptic weights in neuromorphic hardware?
• RQ4 Can system-level workload mapping techniques reduce circuit aging and extend the effective lifetime of neuromorphic accelerators with PCM-based synapses?

Key findings

• DRAM faults at high refresh intervals cause significant classification accuracy degradation in DNN accelerators, even at low error rates, due to bit flips in critical memory regions.
• Circuit faults in the MSB logic cones of MAC units have a disproportionately large impact on DNN accuracy, making them critical targets for reliability hardening.
• Faults in LSB logic cones are more tolerable, but only up to application-specific thresholds; beyond these, accuracy degrades beyond acceptable limits.
• RENUE reduces circuit aging in neuromorphic hardware by 38% on average compared to PyCARL, by optimizing neuron and synapse placement based on aging models.
• eSpine improves the effective lifetime of PCM-based neuromorphic hardware by mapping high-activation synapses to high-endurance PCM cells, reducing aging-related failure rates.
• Parasitic voltage drops in PCM crossbars create significant self-heating asymmetry, leading to endurance variation from 10⁶ to 10¹⁰ cycles across the array, with cells in high-current paths degrading fastest.