[Paper Review] Testable Designs of Toffoli Fredkin Reversible Circuits

Hari Mohan Gaur, Ashutosh Kumar Singh+1 more|arXiv (Cornell University)|Aug 17, 2021

Quantum Computing Algorithms and Architecture22 references4 citations

TL;DR

This paper proposes novel testable design methodologies for Toffoli, Fredkin, and mixed Toffoli-Fredkin reversible circuits using MCT, MCF, and MCTF gates, integrating built-in testability and circuit modifications to minimize testing overhead. The approach achieves up to 75% fault coverage and reductions of up to 60% in gate cost, significantly outperforming state-of-the-art methods in cost metrics and testability efficiency.

ABSTRACT

Loss of every bit in traditional logic circuits involves dissipation of power in the form of heat that evolve to the environment. Reversible logic is one of the alternatives that have capabilities to mitigate this dissipation by preventing the loss of bits. It also have the potential to broaden the horizon of futuristic reckon with its applications to quantum computation. Application of testing strategies to the logic circuits is a necessity that guarantees their true functioning where the researchers are at par with solutions for the upcoming challenges and agreements for reversible logic circuits. Novel methods of designing Toffoli, Fredkin and mixed Toffoli-Fredkin gates based reversible circuits for testability are put fourth in this article. The proposed designs are independent of the implementation techniques and can be brought into real hardware devices after obtaining a stable fabrication environment. The experimentation for the proposed models are performed on RCViewer and RevKit tools to verify the functionality and computation of cost metrics. Fault simulations are carried out using C++ and Java to calculate fault coverage in respective methodologies. The results confirmed that all the presented work outperforms existing state-of-art approaches.

Motivation & Objective

• To address the growing challenge of power dissipation and overheating in nanoscale CMOS circuits by leveraging reversible logic for near-zero energy computation.
• To reduce testing overheads in reversible circuits through built-in testability and efficient circuit modifications, minimizing test data volume and hardware cost.
• To develop scalable, testable designs for key data path elements (DPEs) such as full adders, ripple carry adders, and multipliers with improved cost metrics.
• To establish a comprehensive framework for online and offline testing of reversible circuits using novel fault detection techniques.
• To enable integration of testability into synthesis algorithms, reducing reliance on external testing and minimizing design complexity.

Proposed method

• Proposes new design methodologies using Multiple Controlled Toffoli (MCT), Multiple Controlled Fredkin (MCF), and mixed MCTF gates with inherent testability for single-bit stuck-at faults.
• Introduces circuit modification techniques to enhance fault detection capability without increasing design complexity or test data volume.
• Employs general test sets and deterministic test pattern generation to ensure full fault coverage across all proposed designs.
• Utilizes RCViewer and RevKit tools for functional verification and cost metric computation (gate cost, garbage output, quantum cost).
• Conducts fault simulations using C++ and Java to evaluate fault coverage and testing efficiency across benchmark circuits.
• Applies the framework to design testable DPEs including full adders, ripple carry adders, and multipliers, with performance evaluated on 4–64 bit circuits.

Experimental results

Research questions

• RQ1 How can built-in testability be effectively integrated into MCT, MCF, and MCTF reversible circuits with minimal impact on design cost?
• RQ2 What circuit modification techniques can reduce test data volume while maintaining high fault coverage in reversible logic?
• RQ3 To what extent can the proposed methodologies reduce gate cost, garbage output, and quantum cost compared to existing state-of-the-art approaches?
• RQ4 Can the proposed testable DPEs (e.g., FA, RCA, MUL) achieve significant cost reductions across multiple benchmark configurations?
• RQ5 How effective are the proposed testing methodologies in achieving full fault coverage for single stuck-at faults in reversible circuits?

Key findings

• The proposed testable designs achieve up to 75% fault coverage for MCTF-based methodologies, 61% for MCT, and 49% for MCF-based techniques, with full coverage in all fault models.
• A maximum reduction of 60% in gate cost is achieved for the proposed ALU architecture compared to recent literature, with 44% reduction in multiplier circuits.
• The MCT-based offline testing methodology reduces cost measures by up to 44%, while MCF-based methods achieve a 100% reduction in cost metrics.
• The full adder (FA) design achieves an average cost reduction of 11% across all metrics, while the ripple carry adder (RCA) achieves 12% reduction.
• The proposed framework enables elimination of extra hardware and time for testing by embedding testability during the design phase, minimizing testing overheads.
• The results demonstrate consistent superiority over prior works in all cost metrics, with significant improvements in testability and efficiency for scalable reversible circuits.