[Paper Review] Towards Approaching Total-Power-Capacity: Transmit and Decoding Power Minimization for LDPC Codes.

Karthik Ganesan, Pulkit Grover+2 more|arXiv (Cornell University)|Apr 4, 2015

Error Correcting Code Techniques3 citations

TL;DR

This paper investigates how close regular LDPC codes can get to the fundamental limit of total power (transmit + decoding) in coded communication. Using theoretical bounds and detailed circuit simulations, it shows that minimizing total power requires unbounded transmit power as error probability approaches zero, necessitating increased code and decoding complexity with longer distances or stricter reliability demands.

ABSTRACT

Motivated by recently derived fundamental limits on total (transmit + decoding) power for coded communication, this paper investigates how close regular LDPC codes can get to these fundamental limits. For two decoding algorithms (Gallager-A and Gallager-B), we provide upper and lower bounds on the required decoding power based on models of parallelized decoding implementations. As the target error-probability is lowered to zero, we show that the transmit power must increase unboundedly in order to minimize total (transmit + decoding) power. Complementing our theoretical results, we develop detailed physical models of decoding implementations using rigorous (post-layout) circuit simulations, and use them to provide a framework to search for codes that may minimize total power. Our results show that approaching the total-power channel capacity requires increasing the complexity of both the code design and the corresponding decoding algorithm as the communication distance is increased, or as the target error-probability is lowered.

Motivation & Objective

• To determine how close regular LDPC codes can come to the theoretical total-power limit in coded communication.
• To analyze the trade-off between transmit power and decoding power under decreasing error probability.
• To develop a physical modeling framework for decoding implementations using post-layout circuit simulations.
• To identify code and decoding design strategies that minimize total power consumption.
• To investigate the scaling requirements of code and decoding complexity as communication range or reliability increases.

Proposed method

• Derives upper and lower bounds on decoding power for Gallager-A and Gallager-B decoding algorithms using models of parallelized decoding implementations.
• Employs rigorous post-layout circuit simulations to create accurate physical models of decoding hardware.
• Integrates transmit and decoding power models to evaluate total power consumption across different code and system parameters.
• Uses the combined model to search for LDPC codes that minimize total power under practical hardware constraints.
• Analyzes the asymptotic behavior of total power as target error probability approaches zero.
• Considers the impact of code rate, code length, and implementation parallelism on total power efficiency.

Experimental results

Research questions

• RQ1 How close can regular LDPC codes get to the theoretical total-power limit in coded communication systems?
• RQ2 What is the trade-off between transmit power and decoding power as the target error probability decreases?
• RQ3 How does increasing communication distance or target reliability affect the required complexity of code and decoding design?
• RQ4 What role does hardware implementation efficiency play in minimizing total power consumption?
• RQ5 Can physical circuit models accurately predict the total power scaling of LDPC decoding systems?

Key findings

• As the target error probability approaches zero, the required transmit power increases without bound, making it impossible to achieve finite total power minimization.
• Minimizing total power (transmit + decoding) requires unbounded growth in transmit power, which necessitates increasingly complex code and decoding designs.
• The fundamental total-power limit cannot be approached with finite transmit power when error probability is driven to zero.
• Increasing communication distance or lowering target error probability demands higher code and decoding complexity to approach the total-power capacity.
• Post-layout circuit simulations provide a reliable framework for modeling decoding power and guiding code design for total power minimization.
• The results highlight a fundamental trade-off between reliability, distance, and system complexity in power-constrained coded communication.