Gunhee Han

An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for

This paper examines how real-time information gathered as part of intelligent transportation systems can be used to predict link travel times for one through five time periods ahead (of 5-min duration). The study employed a spectral basis artificial neural network (SNN) that utilizes a sinusoidal transformation technique to increase the linear separability of the input features. Link travel times from Houston that had been collected as part of the automatic vehicle identification system of the T

This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated w

A 2.1 Mpixel 120 frame/s CMOS image sensor with column-parallel ΔΣ ADCs is realized in a 0.13 μm CMOS process. Column-parallel ΔΣ ADC architectures improve the conversion speed while reducing the random noise level as well. Inverter-based SC circuits maximize the power efficiency. This sensor achieves a measured noise floor of 1.9e-, while dissipating 180 mW.

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yiel

An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu$</tex></formula> m CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm,

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13- <formula formulatype="inline" xmlns:mml="http://w

A single-chip CMOS smoke and temperature sensor for use as an intelligent fire detector is proposed. The proposed smoke sensor measures smoke density based on the light-scattering method. The temperature sensor is integrated with the smoke sensor not only to sense heat from a fire but also to compensate for the temperature dependency of the smoke sensor. The prototype chip includes an on-chip photodiode (PD), pixel circuit, correlated double sampling (CDS) circuit, and analog-to-digital converte

Cork is a natural material produced in the Mediterranean countries. Cork stoppers are used to seal wine bottles, Cork stopper quality classification is a practical pattern classification problem. The cork stoppers are grouped into eight classes according to the degree of defects on the cork surface. These defects appear in the form of random-shaped holes, cracks, and others. As a result, the classification cork stopper is not a simple object recognition problem. This is because the pattern featu

This paper presents an improved low-power DeltaSigma modulator, exploiting the class-C inverter and the feedforward topology. The measurement results show 14b dynamic range for a 20kHz bandwidth with 36muW power consumption from a 0.7V supply.

Flicker noise is the most crucial issue in an instrumentation amplifier (IA) for neural recordings because low-frequency neural signals overlap with the frequency of the amplifier's flicker noise. A Chopping technique, often used to reduce the flicker noise, is not desirable for high-impedance input sources due to the charge injection and clock feedthrough from the MOSFETs of the input chopper to the signal source, resulting in a significant increase in the total input-referred noise. Whereas MO

In switched capacitor sigma-delta (ΣΔ) analog-to-digital converters (ADCs), an operational transconductance amplifier (OTA) is the main building block and consumes most of power. This paper proposes that the OTAs can be replaced with class-C inverters for low-power consumption without sacrificing the performance. A second order ΣΔ modulator using class-C inverter technique is fabricated with a 0.35-μm CMOS process, occupies 3024 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink=

Despite the remarkable improvement of hardware and network technology, the inevitable delay from a user's command action to a system response is still one of the most crucial influence factors in user experiences (UXs). Especially for a web video service, an initial delay from click action to video start has significant influences on the quality of experience (QoE). The initial delay of a system can be minimized by preparing execution based on predicted user's intention prior to actual command a

Using a secondary device while viewing a primary device (i.e. TV), or media multitasking, is now common. Numerous researchers and practitioners have attempted to introduce secondary devices into education as a new learning environment providing additional information to the user. However, the learning-related effects of using a second screen remain controversial. This study examined the effects of second-screen-application use on attention, learning performance, and user experience per content r

A general purpose neuro-image processor architecture based on the Multiplexing Neuron Array (MNA) is proposed. It is a pseudo parallel matrix-vector multiplier. The proposed architecture can process not only vector signals but two dimensional signals as well, so various types of neural networks or image processing paradigm can be implemented without any hardware modification. The major advantage is an unlimited expansion capability due to simple routings between processing elements. The architec