Hyungchul Shin

Capacitive touch-screen technology introduces new concepts to user interfaces, such as multi-touch, pinch zoom-in/out gestures, thus expanding the smartphone market. However, capacitive touch-screen technology still suffers from performance degradation like a low frame scan rate and poor accuracy, etc. One of the key performance factors is the immunity to external noise, which intrudes randomly into the touch-screen system. HUM, display noise, and SMPS are such noise sources. The main electrical

The plasma charging stress can be quantified sensitively using differential pair circuits as well as MOSFETs. We have developed a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The model predicts the oxide thickness dependence of plasma charging successfully. A quantitative model of protection diodes for wafer charging effect on future thinner oxides is also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"

This paper presents an analytical noise model for the drain thermal noise, the induced gate noise, and their correlation coefficient in deep-submicron MOSFETs, which is valid in both linear region and saturation region. The impedance field method was used to calculate the external drain thermal noise current. The effect of channel length modulation was included in the analytical equation. The noise behavior of MOSFETs with decreasing channel length was successfully predicted from our model.

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Misunderstanding apparent activation energy ( E aa ) can cause serious error in lifetime predictions. In this paper, the E aa is investigated for sub 20 nm NAND flash memory. In a high-temperature (HT) regime, the interface trap ( N it ) recovery mechanism has the greatest impact on the charge loss. However, the values of E aa and E a (Nit) have a wide difference. Also, the lifetime of the device cannot be estimated by the Arrhenius model due to the E aa roll-off behavior. For the first time, we

Random telegraph noise (RTN) in various devices such as nano-wire, recessed-channel and high-k FET has been studied through various measurement techniques and analysis. By taking into account both effects which are variation of surface potential and poly depletion voltage drop, we proposed a new method for extracting both locations (x <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> , y <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmln

Oxide shorts density obtained from large test capacitors is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. The observed difference in failure rate is explained by the different oxide charging currents for the weak spots in the two devices during plasma processing. This experiment can explain the observed lower density of shorts after plasma processing in ICs, which is composed of many small devices, than in test structures which are lar

A new method for extracting pi-type substrate resistance model of RF MOSFETs based on 3-port measurement is presented. Using NQS and macro-model with extracted substrate components, it is verified that the new substrate resistance model is accurate. Also, temperature dependent macro model is developed. An analytical high frequency thermal noise model for short-channel MOSFETs which covers all operating regions is developed. A simple wide-band model for on-chip inductors on silicon is presented.

The string (STR) with various geometrical profiles in 3-D NAND flash cause the degradation of program efficiency. This is because the program speed differences among WL layers within the STR are caused by the geometrical properties observed through measurement results. In this work, we propose the method to reduce the program speed differences based on a word-line (WL) grouping in terms of threshold voltage (Vth) distribution to compensate for the program start voltage (Vstart). To address vario