Jae-Duk Han

We present BAG2, a framework for the development of process-portable Analog and Mixed Signal (AMS) circuit generators. Such generators are parametrized design procedures that produce schematics, layouts, and verification testbenches for a circuit given input specifications. This paper expands on previous work by introducing a universal AMS circuit verification framework into BAG2, as well as two new layout engines, XBase and Laygo, that enable development of process-portable layout generators. W

A 40-56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifier with delayed pre-charge release is used to boost and pre-condition the h1 feedback signals before

The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up to 56Gb/s per-lane. The CEI-56G-VSR-PAM4 standard [1] defines PAM-4 signaling at 56Gb/s targeting chip-to-module interconnect. Figure 6.3.1 shows the measured S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of a channel resembling such interconnects and the corresponding single-pulse

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/dr

Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sa

The ever-expanding demand for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1]-[4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by minimizing the driver capacitance with pull-up current sources, multiplexing with flexible clock timing control, and employing a fully reconfigurable 5-tap FFE architecture.

LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology. LAYGO supports rapid generation by placing customized templates on process-specific placement grids, thereby encapsulating the design rules and process-specific structures. The templates can be located based o

Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small resi

In this paper, first, we describe an impedance-matched bi-directional multi-drop (IMBM) DQ bus that can handle up to 4 slots, 8 drops at a data-rate of up to 4.8Gb/s. In the case of the SSTL DQ bus, the series resistor of Z0/2 can suppress ringing and attenuate reflections within the chan nel. But, the SSTL DQ bus is still not entirely free from reflections among the slots because the reflection coefficient of the SSTL DQ bus at the stub junctions is -1/4. However, the IMBM DQ bus that we propos

The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decreasing power budgets available for the transceivers push these designs to be extremely energy efficient. To begin addressing this need, recently published NRZ transceivers operating up to 56.5Gb/s with a 1-tap DFE and/or CTLE [1,2] in 28-40nm CMOS processes have been demonstrated for <;20dB loss channels with ener

This paper demonstrates a signal analysis systemon-chip (SoC) consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the application core and the accelerators are design instances produced through an agile design-space exploration process by generators that allow for a wide range of parameter configurations. The signal processing chain consists of generated instances of a time-interleaved analog-to-digital converter (ADC) follo

Supporting a wide operating range for industrial-standard backward-compatible transmitters often results in energy inefficiency. This paper describes an energy-efficient voltage-mode-serializing transmitter with an operating range of up to 32 Gb/s. The proposed transmitter uses a programmable internal supply to set the voltage level for various data rates optimally, thus improving overall energy efficiency. Output swing and pre-emphasis levels are largely adjustable while the constant output imp

To match pace with the performance enhancement of computing systems for data-centric applications, data rates of high-speed I/O transceivers for the computing systems are increasing beyond 100Gb/s/lane. Four-level pulse-amplitude modulation (PAM-4) signaling has been widely adopted due to its energy efficiency and high data rate under finite channel bandwidth [1–4]. To overcome the timing constraints related to the dynamic power consumption and horizontal eye margin, transmitters with higher mod

This article presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology to produce optimal layouts more efficiently. Layout templates and grids are dynamically created and adjusted during the generation phase to provide more reusability and flexibility. Virtual instances are used to encapsulate the dynamically generated layout structures. Internal node probes embedded in the dynamic templates ca

A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three