Jae-Yun Sim

An all-digital PLL for wireline applications is designed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2× time amplifiers, the TDC efficiently generates the exponent-only information for fractional time difference. To improve linearity in a wide input range, a replica-based self-calibration scheme is applied to the time amplifier. The TDC, implemented in a 0.18 μm CMOS, shows the minimum resolution of 1.25 ps with a total conversi

A time-based (TB) receiver (RX) with a 2-tap TB decision feedback equalizer (DFE) is proposed for mobile DRAM interface. The TB RX consists of a voltage-to-time converter (VTC), a TB DFE, and a time comparator. The VTC converts the RX input voltage to a time difference between two VTC outputs by using the difference in clock-to-Q delays between two latches with different input offset voltages. The TB DFE inserts an additional delay to one of the two VTC outputs and bypasses the other VTC output

A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of ~10 dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential

A differential transceiver achieves a 40 mVppd channel signal-swing, a 9 mVppd receiver (RX) input sensitivity, and a 0.59 pJ/b energy efficiency at 9 Gb/s with a 12" FR-4 channel. A current-integrating TIA (CI-TIA) is proposed as a RX pre-amplifier to enhance the RX input sensitivity by increasing the voltage gain of the CI-TIA to around 18 at 9 Gb/s. The RX circuit alone works up to 11 Gb/s with a 1" FR-4 channel. A voltage-mode pre-emphasis equalizer is combined with a current-mode logic (CML

A single-ended transmitter (Tx) is proposed to compensate for the crosstalk-induced jitter (CIJ) of coupled microstrip lines by subtracting a mimicked crosstalk waveform from data signal at Tx during the data transition time, depending on the data transition of an adjacent line. Since the CIJ component is proportional to the time derivative of data signal, the mimicked crosstalk waveform subtracted at Tx cancels the CIJ at receiver (Rx) for the linearly changing data signal with time. As a by-pr

In high-speed communication with a data rate of multi-Gb/s, the crosstalk noise induced by electromagnetic coupling is becoming a significant noise source, requiring careful considerations in the design of transceiver circuits as well as physical dimension of the transmission lines. When an input voltage of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> is applied to one of two parallel transmission lines, the induced voltages at the vict

A switched-diode termination (SDT) is proposed to implement a low-power transceiver circuit for on-chip single-ended signaling through a through-silicon via (TSV). The channel signal swing is limited to 40 mV by the SDT to reduce the transmitter (TX) power. An inverter-cascade amplifier is used to reduce the receiver (RX) power. The SDT consists of an nMOS diode and a pMOS diode, which are connected in a series between power rails through the RX input node. Only one of these two diodes is switch

Emerging demands on ultra-low-power wireless sensor platform have presented challenges for nano-watt design of various circuit components. Clock management unit, as an essential block, is one of the most actively researched blocks. It is required to distribute various frequency ranges for energy-optimal operation, e.g., Hz for internal timer [1], kHz for global clock [2], and MHz for fast data transmission or intensive signal processing [3]. However, free-running oscillators are seriously affect

Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed interface for transmission of image data [1]. To reduce transmitter power in single-ended transceivers, both the supply voltage and the signal swing are reduced: 0.8V and 200mV, or below [2]. However, with a small signal swing the low-supply voltage limits the maximum data rate tha

TSV is considered to be the next industry standard for chip interconnects because of huge number of I/O pins and high frequency capability. However, TSV is not readily available to develop interface circuits. An on-chip TSV emulation is presented by using a horizontal metal bar surrounded by a horizontal metal ring on a silicon chip with a 0.13-µm CMOS process. The resistance and capacitance of emulated TSVs and the substrate resistance are extracted as an HSPICE W-element model through measurem

A high-voltage DC bias generator chip is designed to address the scalability challenges of ion trap systems. The circuit employs a single digital-to-analog converter (DAC) to generate 64 channel outputs using time-division multiplexed driving. The chip, fabricated using 180 nm BCDMOS process, produces 64 DC voltages in a range of -10V to 16V at 4 Kelvin(4K) with an 11.06 bit resolution. The chip is verified with a trap of ${ }^{40} \mathbf{C a}^{+}$ ions, showing successful operations of capturi

This paper presents a 20-Gb/s/line current-mode transceiver for dense short-reach on-chip interconnect. The transceiver achieves a systematic crosstalk cancellation (XTC) by balancing the crosstalk induced by capacitive and inductive coupling. As a receiver frontend, a current-sensing amplifier is designed with an optimum input resistance value for XTC. Without any additional circuits for XTC and equalization, the transceiver implemented in a 40nm CMOS technology shows an energy efficiency of 24

This brief presents an 8-bit parallel transceiver for low-power memory interface with a current-regulated voltage-mode driver and a clock and data recovery performing both bit recovery and byte alignment. Sharing a current source by output drivers enables voltage swing control without any regulator circuit while holding the benefits of low-power voltage-mode driving. In the receiver, with only one phase rotator in a globally shared phase-locked loop, a narrow-range delay line in each deskewing p

This paper explains modeling and analysisof RC-dominant wires for high-speed wirelinetransceiver design. A closed form formula derivedfrom telegrapher’s equation accurately describes afrequency response of an RC-dominant wire, yet it issimple and intuitive for designers to easily understanddesign trade-offs without a complex numericalequation solver. This paper explains how the model isderived and how it can help designers in exampletransceiver designs.

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37 dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35 m CMOS process. This