Joonyeol Lee
Sungkyunkwan University · Engineering
About the Lab
Professor Joonyeol Lee's research lab specializes in high-speed integrated circuit design, with a focus on advanced signaling techniques and clock and data recovery (CDR) architectures for next-generation memory and communication systems. The lab develops energy-efficient, high-bandwidth transceivers and adaptive CDR solutions that enable robust data transmission at multi-gigabit data rates. Key research directions include ground-referenced signaling (GRS), feed-forward equalization, dynamic frequency and voltage scaling, and jitter tolerance optimization in advanced CMOS processes. The lab emphasizes practical, area- and power-efficient implementations for real-world applications in high-speed interfaces and memory subsystems.
Research Overview
Research Output Trend
Figures are computed from collected data and may differ slightly.
Selected Papers
3A referenceless single-loop clock and data recovery (CDR) with a 6.4-11-Gb/s capture range is presented. A dynamic bandwidth control (DBWC) technique for reducing the frequency-acquisition time and adaptive loop gain control (ALGC) for optimizing the jitter tolerance are described in detail. In addition, a cycle-slip detector (CSDET) with a consecutive-edge selector (CES) is proposed to improve the accuracy of the frequency detection. Fabricated in a 28-nm CMOS process, the proposed CDR has a fr
This paper describes a ground-referenced signaling (GRS) transceiver with a 3-tap feed-forward equalizer and low frequency mode. In the prototype transceiver, four DQ data lanes share one DQS clock-forwarding lane. To accommodate dynamic voltage and frequency scaling, the proposed transmitter operates in two modes depending on the frequency. The feed-forward equalizer's tap coefficients can be tuned by the pre-charged voltage levels and the number of activated segments. Fabricated in a 28-nm CMO
Research Areas
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