Jooyeon Kim
Ulsan National Institute of Science and Technology · Engineering
About the Lab
Professor Jooyeon Kim's research lab specializes in computer architecture and integrated circuit design, with a strong focus on low-power and high-performance digital systems. The lab investigates advanced clock network synthesis techniques, including useful clock skew scheduling, adjustable delay buffer (ADB) allocation, and clock spine network design, to enhance timing robustness and energy efficiency in multi-power-mode environments. Additionally, the lab explores machine learning applications in predicting operational risks in complex systems, such as container port accidents, demonstrating interdisciplinary research spanning computer engineering and data science. Their work bridges theoretical optimization with practical implementation challenges in modern VLSI design and system-level reliability.
Research Overview
Research Output Trend
Figures are computed from collected data and may differ slightly.
Selected Papers
15The occurrence of accidents at container ports results in damages and economic losses in the terminal operation. Therefore, it is necessary to accurately predict accidents at container ports. Several machine learning models have been applied to predict accidents at a container port under various time intervals, and the optimal model was selected by comparing the results of different models in terms of their accuracy, precision, recall, and F1 score. The results show that a deep neural network mo
Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimiz
It has been reported that hepatic polyploidization is closely linked to the progression of NAFLD. Here, we showed that the genetic depletion of hepatic RORα in mice accelerated hepatocyte polyploidization after high-fat diet feeding. The mechanism could be the RORα-mediated repression of E2f7 and E2f8, key transcription factors for DNA endoreplication. Thus, preservation of genome integrity by RORα could provide a new insight for developing therapeutics against the disease.
Contrary to the bounded clock skew scheduling, which controls the clock signal arrival times of flip-flops (FFs) so that all clock skews are within a given bound, the useful clock skew scheduling exploits the time borrowing between signal paths by controlling the clock times in a way to meet the timing constraints of the individual signal paths, thus enabling a further improvement of clock frequency. However, even though there are many works on the useful clock skew scheduling, most of them are
Clock tree and clock mesh are two extreme structures of clock networks. Clock tree is good at saving clock wires and power, but is vulnerable to clock skew variation. On the other hand, clock mesh is good at mitigating clock skew variation, but spends considerable wires and power. Well known intermediate structures are clock tree with cross links and clock spine. This work addresses the problem automating the synthesis of clock spine networks. Unlike the clock tree with links between clock nodes
This paper proposes a graph-based algorithm for solving the adjustable delay buffer (ADB) allocation problem optimally under useful clock skew scheduling. Our algorithm supports additional features: extending the optimality to the allocation of ADBs with quantized delay values, extending the optimality to the allocation of ADBs with delay upper bound, and extending to the consideration of the delay variability of clock buffers. In addition, we propose two acceleration techniques for speeding up
We investigated the electrical properties of the In–Ga–Zn–O (IGZO) film under light illumination. We measured the photoconductivity of a-IGZO thin film under light illumination with various intensities. We extracted the photoexcitation activation energy and dark relaxation activation energy through extended stretched exponential analysis. Dark relaxation characteristics, which are related to the recombination process, show longer time constant, τ, larger effective activation energy E ac , and lo
We investigated the photo responses of an amorphous indium gallium zinc oxide (a-IGZO) thin film under light illumination with various wavelengths and intensities. By using the measured photo-conductivities of a-IGZO thin films, we extracted the photo excitation activation energy and dark relaxation activation energy through extended stretched exponential analysis. The stretched exponential analysis was found to describe well both the photoexcitation and the dark-relaxation characteristics. Thes
In this study we characterized the transient photocurrent responses in solution-processed amorphous zinc-tin-oxide (a-ZTO) thin films measured under light illumination with a wavelength of 400 nm at different temperatures. By using the temperature-dependent photoconductivities of a-ZTO thin films, we extracted the activation energies (E ac ) of photo-excitation and dark relaxation through an extended stretched exponential analysis (SEA). The SEA was found to describe well the dark relaxation cha
A high power MOSFET switch based on a 0.35 <TEX>${\mu}m$</TEX> CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 <TEX>${\mu}m$</TEX>-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been
Clock tree and clock mesh are two extreme structures of clock networks. Clock tree is good at saving clock wires and power, but is vulnerable to clock skew variation. On the other hand, clock mesh is good at mitigating clock skew variation, but spends considerable wires and power. Well known intermediate structures are clock tree with cross links and clock spine. This work addresses the problem automating the synthesis of clock spine networks. Unlike the clock tree with links between clock nodes
This paper investigated the photo response behavior of amorphous indium gallium zinc oxide (a-IGZO) thin films, identifying three distinct photoconductivity types corresponding to different oxygen vacancy concentrations: Type I (low vacancy density), Type II (intermediate density), and Type III (high vacancy density). The results reveal that the photoconductive properties of a-IGZO are massively influenced by oxygen vacancy concentration, which can be precisely controlled through vacuum annealin
Research Areas
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