Minsu Jeong

A UHF mobile single chip RFID reader is implemented in 0.18μm CMOS process. Developed IC achieves DA output power of 3 dBm, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OIP3</i> of 14.8 dBm, phase noise of -100 dBc/Hz at 100 kHz offset, noise figure of 35.5 dB for talk mode, 6.2 dB for listen before talk (LBT) mode, and current consumption of 108 mA from a 1.8 V supply. With an external PA, Tx output generates output power of 27 dBm with <i xmlns:m

For a few years, new mobile broadcasting services were launched in Korea, Japan, Europe and China. The mobile broadcasting markets are maturing rapidly for applications such as mobile cellular phones, car navigation, PMP and so on. The market drives low-cost, low-power and small size significantly for mobile applications and drives multiple functionality and multiple bands [1]. To meet the market requirements, more integration of system blocks and functionality is needed. To achieve this goal, t

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology for WLAN CMOS PAs is proposed to obtain broadband performances with a compact area using the wafer-level package technology. To achieve a highly linear output power with high efficiency across a 1-GHz bandwidth in a 5G-band PA, a reconfigurable interstage matc

A direct-conversion satellite tuner-demodulator IC is realized using 0.18/spl mu/m CMOS technology. The IC down-converts a 950-2150MHz satellite broadcasting signal to base band and demodulates the signal to an MPEG data stream. The IC conforms to both DVB-S and DSS standards. Experimental results show a 9dBm IIP3 while consuming 230mA from 1.8V supply.

A new digital pixel driving scheme is presented for reducing power in the column-line drivers in a single-pulse-PWM-based display. Rather than updating the digital pixel memory value for every access of the memory, the proposed driving scheme utilizes the property that there are only two level transitions in a single-pulse PWM for representing a digital value. With the use of AND-embedded SRAM pixel memory and simple logic controlling the AND gates, this minimizes the number of column-line signa

This paper provides a complex band-pass filter (BPF) for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner with I/Q gain and phase mismatch calibration. This calibration can be implemented in the first stage of complex BPF using feed-through resistor calibration scheme. The automatic tuning circuit with programmable clock is also presented. The measurement results show 1.536 MHz bandwidth with 2.048 MHz IF center frequency and 50 dB

A new SRAM-based pixel circuit is presented for use in a high-voltage digitally-driven pixel array in a micro-display panel. The pixel circuit is based on the standard 6T SRAM structure, but uses two more transistors of which gate dc-bias is controlled to adjust the pull-up strength of the inverters in the SRAM. This allows the pixel circuit to be operated with low-voltage row- and column-line signals while holding the stored logic in a high-voltage level. As a result, power and area of the pixe

A 0.18μm CMOS dual-band low-IF mobile-TV tuner IC for T-DMB/DAB that supports Band-III and L-band is presented. By modifying a few metals and via masks, the IC can support VHF and UHF bands for ISDB-T partial reception. The chip meets all the specifications of both applications with a sensitivity of <-98dBm while consuming 100 mW from a 1.8V supply and occupying 3.4 X 3.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated with a standard 40-nm CMOS process. In comparison with a parallel combining transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, and does so with a compact die area. With an 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, the fully integrated dual-mode PA achieves 19.

This paper provides a channel select low-pass filter with automatic cut-off frequency tuning circuit for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner IC. This filter has 1.58MHz cut-off frequency, 20dB and 65dB stop band attenuation at 1.9MHz and 2.4MHz, respectively. The in-band IIP3 is -8.4dBV and 1dB desensitization is satisfied for 490mVpp interferer at 1.7MHz frequency offset. By using simple automatic tuning technique, les

This paper proposes a fully integrated linear wireless LAN (WLAN) CMOS power amplifier (PA) with parallel-combined transistors and selective adaptive biasing. An adaptive bias circuit is applied to one of the parallel-combined transistors to take advantage of both the parallel-combined transistor method and adaptive biasing at the target output power region. By using the proposed biasing, the linear output power can be maximized, resulting in a higher power added efficiency (PAE). The experiment

A CMOS analog front-end processor for a 4x speed CD-ROM is designed and fabricated in a 0.8-μm process. The IC consists of RF amplifiers, pulse reshaping circuits, an automatic power control circuit for laser diode, and a servo control signal generator which includes track and focus error detecting circuits. Experimental result shows that its RF performance is enough for 8x speed CD-ROM. The circuit enables to design a true one chip 4x speed and 8x speed CD-ROM or DVD player in digital CMOS proc

A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with two auxiliary transistors extends the linear region further compared with MGTR with single auxiliary transistor. Second, resistive source degeneration significantly suppresses the unwanted 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -harmonic feedback effect caused by an indu

A low power high linear transmitter for mobile WiBro and WiMAX is developed. The transmitter is fabricated in a 0.18 μm 1P6M CMOS process for low power characteristics and SoC compatibility. To achieve high linearity performance with low power consumption, the transmitter employs new linearization methods. Linear transconductor is used for the transmitter mixer. The transconductor utilizes a negative feedback amplifier and a current mirror amplifier (CMA). In addition, a multiple-gated transisto

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method