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Sam H. Noh

Ulsan National Institute of Science and Technology · Computer Science

About the Lab

Professor Sam H. Noh's research lab focuses on computer system optimization, particularly in memory hierarchy design, non-volatile main memory technologies, and efficient data management in file systems. The lab explores hybrid memory architectures—especially those combining DRAM and emerging non-volatile memories like PCM and STT-MRAM—to address performance and endurance challenges. Key research directions include intelligent buffer management, flash translation layer design, and journaling techniques that leverage non-volatile memory for faster and more reliable storage systems.

non-volatile memoryhybrid memorybuffer managementflash memoryfile system

Research Overview

Papers
162
Total Citations
4,218
Papers (5y)
16
Primary Field
Computer Science

Research Output Trend

Figures are computed from collected data and may differ slightly.

Publications per year (5y)
16total
2022
2023
2024
2025
2026
Citations per year (5y)
45total
20222023202420252026

Selected Papers

15
1
Article|693 citations·2002
A space-efficient flash translation layer for CompactFlash systems
Jesung Kim, Jong‐Min Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho
SJR Q1IEEE Transactions on Consumer Electronics

Flash memory is becoming increasingly important as nonvolatile storage for mobile consumer electronics due to its low power consumption and shock resistance. However, it imposes technical challenges in that a write should be preceded by an erase operation, and that this erase operation can be performed only in a unit much larger than the write unit. To address these technical hurdles, an intermediate software layer called a flash translation layer (FTL) is generally employed to redirect logical

Computer Networks and CommunicationsComputer Science
2
Article|583 citations·2001
LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies
Dong‐Hee Lee, Jongmoo Choi, Jong‐Hun Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong Sang Kim
SJR Q1IEEE Transactions on Computers

Efficient and effective buffering of disk blocks in main memory is critical for better file system performance due to a wide speed gap between main memory and hard disks. In such a buffering system, one of the most important design decisions is the block replacement policy that determines which disk block to replace when the buffer is full, In this paper, we show that there exists a spectrum of block replacement policies that subsumes the two seemingly unrelated and independent Least Recently Us

Computer Networks and CommunicationsComputer Science
3
Article|277 citations·1999
On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies
Donghee Lee, Jongmoo Choi, Jong‐Hun Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong Sang Kim

article Free Access Share on On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies Authors: Donghee Lee Dept. of Information Engineering, Cheju National University, Korea and Department of Computer Engineering, Seoul National University, Seoul 151-742, Korea Dept. of Information Engineering, Cheju National University, Korea and Department of Computer Engineering, Seoul National University, Seoul 151-742, KoreaView Profile

Computer Networks and CommunicationsComputer Science
4
Article|169 citations·2013
Unioning of the buffer cache and journaling layers with non-volatile memory
Eunji Lee, Hyokyung Bahn, Sam H. Noh
File and Storage Technologies

Journaling techniques are widely used in modern file systems as they provide high reliability and fast recovery from system failures. However, it reduces the performance benefit of buffer caching as journaling accounts for a bulk of the storage writes in real system environments. In this paper, we present a novel buffer cache architecture that subsumes the functionality of caching and journaling by making use of non-volatile memory such as PCM or STT-MRAM. Specifically, our buffer cache supports

Computer Networks and CommunicationsComputer Science
5
Article|149 citations·2013
CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures
Soyoon Lee, Hyokyung Bahn, Sam H. Noh
SJR Q1IEEE Transactions on Computers

Phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy of future computer systems. However, PCM has two critical weaknesses to substitute DRAM memory in its entirety. First, the number of write operations allowed to each PCM cell is limited. Second, write access time of PCM is about 6–10 times slower than that of DRAM. To cope with this situation, hybrid memory architectures that use a small amount of DRAM together with PCM have b

Hardware and ArchitectureComputer Science
6
Article|136 citations·2000
A low-overhead high-performance unified buffer management scheme that exploits sequential and looping references
Jong Min Kim, Jongmoo Choi, Jesung Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong Sang Kim
Operating Systems Design and Implementation

In traditional file system implementations, the Least Recently Used (LRU) block replacement scheme is widely used to manage the buffer cache due to its simplicity and adaptability. However, the LRU scheme exhibits performance degradations because it does not make use of reference regularities such as sequential and looping references. In this paper, we present a Unified Buffer Management (UBM) scheme that exploits these regularities and yet, is simple to deploy. The UBM scheme automatically dete

Computer Networks and CommunicationsComputer Science
7
Article|112 citations·2012
Caching less for better performance: balancing cache size and update cost of flash memory cache in hybrid storage systems
Yongseok Oh, Jongmoo Choi, Dong‐Hee Lee, Sam H. Noh
File and Storage Technologies

Hybrid storage solutions use NAND flash memory based Solid State Drives (SSDs) as non-volatile cache and traditional Hard Disk Drives (HDDs) as lower level storage. Unlike a typical cache, internally, the flash memory cache is divided into cache space and overprovisioned space, used for garbage collection. We show that balancing the two spaces appropriately helps improve the performance of hybrid storage systems. We show that contrary to expectations, the cache need not be filled with data to th

Computer Networks and CommunicationsComputer Science
8
Article|5 citations·2013
Towards greener data centers with storage class memory
In Hwan Doh, Young J. Kim, Eunsam Kim, Jongmoo Choi, Dong-Hee Lee, Sam H. Noh
SJR Q1Future Generation Computer Systems
Information SystemsComputer Science
9
Article|4 citations·2003
Improving massively data parallel system performance with heterogeneity
Sam H. Noh, Klaudia Dussa-Zieger

The authors introduce a new type of combined SIMD/MIMD (single-instruction multiple-data/multiple-instruction multiple-data) architecture called a hybrid system. The hybrid system consists of two components. The first component is massively parallel and consists of a large number of slow processors that are organized in an SIMD architecture. The second component consists of only a few fast processors (possibly only one) which are organized in an MIMD architecture. The authors contend that a hybr

Hardware and ArchitectureComputer Science
10
Article|2 citations·1992
The RPT Parallel Gaussian Elimination Algorithm.
Sam H. Noh, Soo‐Mook Moon, Ashok K. Agrawala
Proceedings of the International Conference on Parallel Processing

Cancer in inguinal hernias is rare. The author reports the first case of thymoma metastatic to an inguinal hernia sac (saccular) and the 13th case of colon cancer in an inguinal hernia (intrasaccular); both cases presented clinically as incarcerated hernias.

Artificial IntelligenceComputer Science
11
Article|2 citations·1999
A Heterogeneous Mixed-Mode Execution Model for Massively Parallel Systems
Sam H. Noh, Klaudia Dussa-Zieger, Ashok K. Agrawala
SJR Q1Journal of Parallel and Distributed Computing
Hardware and ArchitectureComputer Science
12
Article|2 citations·1989
An empirical study of the effect of granularity on parallel algorithms on the connection machine
Sam H. Noh, Dipak Ghosal, Ashok K. Agrawala
Computer Networks and CommunicationsComputer Science
13
Article|1 citations·2018
Editor-in Chief Letter
Sam H. Noh
SJR Q2ACM Transactions on StorageOA

No abstract available.

Economics and EconometricsEconomics, Econometrics and Finance
14
Article|1 citations·2003
Performance prediction of message passing SIMD multiprocessor systems
Sam H. Noh, Ashok K. Agrawala

The paper focuses on two points: (1) the prediction of the execution signature of massively parallel applications prior to execution/implementation based on a more informative characterization of the workload, and (2) the definition of a more general form of speedup and efficiency. The systems considered are of SIMD message passing paradigm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hardware and ArchitectureComputer Science
15
Article|0 citations·2016
Session details: Session 6A: Reliability and Debugging II
Sam H. Noh
ACM SIGPLAN Notices

No abstract available.

Economics and EconometricsEconomics, Econometrics and Finance

Research Areas

Computer Networks and CommunicationsHardware and ArchitectureComputer Vision and Pattern RecognitionInformation SystemsEconomics and EconometricsElectrical and Electronic Engineering

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