Sang Ho Lee

Hafnia-based ferroelectric materials are recently drawing a significant attention for future electronic devices; however, there is a need to further enhance their functionality for practical applications. Especially, an imprinting effect has been regarded as a defect to be reduced in ferroelectrics; yet, it can be positively applied to various electronic devices with the functionality of self-rectifying behavior and threshold voltage adjustment. For the first time, we report a high imprinting ef

In this work, we propose a structural approach to mitigate device-to-device variation and performance degradation of ferroelectric (FE) field-effect transistors (FeFETs) due to the inhomogeneity of FE and dielectric (DE) phases of the FE layer. We found that by inserting a floating gate below the FE layer, the polarization effect of FE grains is equalized, thus suppressing the formation of an undesired current percolation path through the channel of the FeFET. This also results in a wider memory

In this work, we demonstrate a novel approach to superior multilevel-cell (MLC) ferroelectric field-effect transistor (FeFET) with a large memory window (MW) and negligible <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> variation toward MLC operation. We realized high ferroelectricity in a relatively thick HZO ferroelectric (FE) layer for FeFET with a large MW [MW <inline

In this study, we investigated the impact of unstable and stable interface trap charges (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{\text {it}}\text {)}$ </tex-math></inline-formula> on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {S}}$ </tex-math></inline-formula> switching in metal-ferroelectric–ins

This letter introduces a novel methodology to improve the thermal stability of Zr:HfO2 (HZO) ferroelectric (FE) materials by adding AlN as the middle interlayer (IL) between HZO. Adding AlN to HZO improves the thermal stability of FE layers in three ways. Initially, the growth of grains and the formation of the dielectric monoclinic (m-) phase are kinetically suppressed in the HZO when subjected to a subsequent thermal budget (TB) after crystallization annealing for the formation of FE layers. T

We reveal the origin of disturbance issues in ferroelectric FETs (FeFETs) with a metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) stack. To achieve both low-voltage operation and disturbance immunity, we introduce a multi-functional <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{TiO}_{2}$</tex> layer, positioned between the G.IL and FE layer. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink

The morphotropic phase boundary (MPB), which arises from the combination of antiferroelectric and ferroelectric phases, demonstrates the highest dielectric constant ( κ ) compared to other phases. This emphasizes its potential as a leading contender for dielectric films in future dynamic random access memory (DRAM) capacitors. MPB‐based high‐ κ materials using hafnia have shown a trade‐off between equivalent oxide thickness (EOT) and leakage current density ( J leak ) when the crystallization te

In recent years, following trends in developing semiconductors, extensive research has been conducted to develop a hafnia‐based ferroelectric field effect transistor (FeFET) memory. However, its fundamental endurance limitation, which stems from early degradation of the gate insulator, has been a major obstacle to the development of FeFETs, with no clear solution despite attempting various approaches to high‐speed and high‐reliability FeFETs. Herein, a novel metal–ferroelectric–metal–insulator–s

The concept of negative capacitance (NC), originating from the intrinsic energy configuration of HZO ferroelectrics, has been predominantly utilized in logic transistors to achieve a steeper Id-Vg characteristic. Departing from these conventional approaches, we have developed an NC-NAND flash memory by integrating the NC phenomenon into the blocking oxide layer of conventional NAND flash memory. By leveraging the capacitance boosting effect of the NC-integrated blocking oxide (BO) layer, we can

The ferroelectric (FE) NAND flash, featuring metal-interlayer-FE-interlayer-silicon (MIFIS) gate stacks, leverages both charge trapping and polarization (P) switching to achieve a broad memory window (MW) and low operation voltage. These remarkable advancements establish it as a viable contender for future NAND flash technologies. However, the read-after-write-delay (RAWD) problem during program/erase (PGM/ERS), caused by channel-injected interface trapped charges (<inline-formula xmlns:mml="htt

Hafnia-based ferroelectrics (FEs) can be stabilized via careful engineering, both kinetically and thermodynamically. Especially, the fast cooling process has been regarded as an efficient approach for kinetically maximizing the phase transition to the orthorhombic (o-) phase from the tetragonal (t-) phase, which stabilizes thermodynamically during crystallization annealing. However, accurately controlling the cooling period for fast cooling procedures is challenging, resulting in unreliable and

This study employs analytical simulation to illustrate the beneficial correlation between interface trapped charge and spontaneous polarization (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {S}}$ </tex-math></inline-formula>) switching behavior in the MIFIS gate stack. We found that there is a positive interaction between charge trapping and polarization switching, comprising three sequential pro

We present a device-level integration strategy for implementing negative-capacitance (NC) in charge trap flash (CTF) memory to achieve low programming voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PGM</inf>) and enhanced reliability. Robust ferroelectricity and active NC behavior are realized in sub-3.5 nm HfZrO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (HZO) by engineering an u

Charge trap flash (CTF) memory has emerged as a key solution for high-density nonvolatile memory. However, the high operating voltage of CTF memory leads to critical reliability issues, such as cell-to-cell interference and dielectric breakdown, limiting further pitch size scaling in 3D architectures. Here, we report a negative capacitance charge trap flash (NC-CTF) memory that exhibits remarkable operation efficiency by using the NC-induced capacitance boosting effect of Hf 0.5 Zr 0.5 O 2 (HZO)

Metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) ferroelectric field-effect transistors (FeFETs) are attractive for large memory window (MW) and low-voltage FE NAND operation. Nevertheless, its fundamental operating principle also makes the device vulnerable to threshold voltage (Vth) shift under repeated disturb bias, which remains a major obstacle to array-level reliability. In this study, we employ a TiO2 nanolayer (NL) at the upper interface of the HZO FE