Seung‐Tak Ryu

This paper presents transformer-based self-starting boost converter architecture with low-power maximum power point tracking (MPPT) control for low-voltage thermoelectric generator applications. The minimum working voltage of the proposed boost converter is 40 mV with oscillation through a positive feedback loop formed by a native MOS and transformer. The oscillation autonomously starts up by thermal noise and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1

A highly-porous, binder free 3D-NiCo₂O₄/Ni nanostructure on the Ni-wire was fabricated for flexible fiber supercapacitors. The fabricated device exhibited enhanced capacitance, high efficiency, good cycling stability, and flexibility.

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances th

A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different designated functions, SIG-DAC and REF-DAC, are implemented to make the structure compact and to eliminate the sampling skew issue. Use of a nonbinary decision scheme with decision redundancies not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuations and comparator offset variations. The proposed dynamic register and

This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-a

Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 muW/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp

Capacitive touch-screen panels (TSPs) are widely used in recent high-end mobile products on the basis of their high quality of touch features, as well as superior visibility and durability [1-5]. Capacitive TSPs can be classified into self-capacitance [1,2] or mutual-capacitance [3-5] types, according to the sensing mechanism. Compared with the self-capacitance types, which offer low cost and high scan frequency from the simple line-sensing scheme, the mutual-capacitance types, which read out al

A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic comparators by half. The reduced number of comparators lowers power consumption, load capacitance to the T/H circuit, and the overhead of comparator calibration. The measured peak INL and DNL after comparator calibration are 0.74 and 0.49 LSB, respectively. The measured SNDR and SFDR are 31.2 and 38.3 dB, respectively, with a 2.02-GHz input at 4

By taking advantage of the merits of the low power consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1-3]. However, many error sources in the 2b/cycle SAR ADCs, such as mismatches between DACs and comparators, and the signal-dependent errors from comparators, namely kickback noise and offset, make it difficult to achieve high resolution. To date, pure 2b/cycle str

The capacitor mismatch in a 1.5-b/stage pipelined ADC is background calibrated in the analog domain using a pseudorandom (PN) dithering concept. The reference voltage added/subtracted during the normal operation is used as a dither to PN-modulate the mismatch error so that it can be embedded into the residue and be recovered later by correlating with the same PN sequence. Six MSB stages are simultaneously calibrated using separate zero-forcing feedback loops. The signal-subtracted analog PN corr

In this paper, a compensation technique for realizing a precise decibel-linear CMOS programmable gain amplifier (PGA) is described. The proposed PGA, employing an auxiliary pair, not only retains a constant current density but also offers a gain-independent bandwidth (BW). For verification, a compact PGA (0.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) is fabricated using a 0.13-μm CMOS process and measured. The measured gain contro

With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a

A compact low-power on-chip power-on reset circuit with a brown-out detection capability is presented. With a pico-farad-order on-chip MOS capacitor, a long reset time is achieved. A prototype design implemented in a 0.18-μm CMOS process provides a reset signal with duration of hundreds of milliseconds. The embedded brown-out detection circuit can detect the event, as long as the brown-out duration is longer than the millisecond range. The chip consumes only 1 μA under a 1.8-V supply and occupie

This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout (A-readout) scheme reads the signal difference between two pixels located next to each other (Apixel) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by the A-window checking, the proposed A-readout scheme can reduce the effective number of decision cycle