Seyoung Kim

We fabricate and characterize dual-gated graphene field-effect transistors using Al2O3 as top-gate dielectric. We use a thin Al film as a nucleation layer to enable the atomic layer deposition of Al2O3. Our devices show mobility values of over 8000 cm2/V s at room temperature, a finding which indicates that the top-gate stack does not significantly increase the carrier scattering and consequently degrade the device characteristics. We propose a device model to fit the experimental data using a s

Using a structure consisting of two, independently contacted graphene single layers separated by an ultrathin dielectric, we experimentally measure the Coulomb drag of massless fermions in graphene. At temperatures higher than 50 K, the Coulomb drag follows a temperature and carrier density dependence consistent with the Fermi liquid regime. As the temperature is reduced, the Coulomb drag exhibits giant fluctuations with an increasing amplitude, thanks to the interplay between coherent transport

We describe a technique which allows a direct measurement of the relative Fermi energy in an electron system by employing a double-layer heterostructure. We illustrate this method by using a graphene double layer to probe the Fermi energy as a function of carrier density in monolayer graphene, at zero and in high magnetic fields. This technique allows us to determine the Fermi velocity, Landau level spacing, and Landau level broadening. We find that the N=0 Landau level broadening is larger by c

We demonstrate a CMOS-compatible, metal-oxide based Electro-Chemical Random-Access Memory (MO- ECRAM) for high-speed, low-power neuromorphic computing. The device demonstrates symmetric and linear conductance update, large on/off ratio and good retention while also withstanding high temperature treatments necessary for BEOL compatibility. Resistive switching in MO-ECRAM is observed with voltage pulses down to 10 ns and scales exponentially with voltage pulse amplitude, enabling parallel array op

Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and pr

We investigate the transverse electric field ($E$) dependence of the $\ensuremath{\nu}=0$ quantum Hall state (QHS) in dual-gated graphene bilayers in high magnetic fields. The longitudinal resistivity ${\ensuremath{\rho}}_{xx}$ measured at $\ensuremath{\nu}=0$ shows an insulating behavior which is strongest in the vicinity of $E=0$, as well as at large $E$ fields. At a fixed perpendicular magnetic field ($B$), the $\ensuremath{\nu}=0$ QHS undergoes a transition as a function of the applied $E$,

Abstract Cross‐point arrays of synaptic devices have been investigated as a core platform for neuromorphic computing architectures. To achieve a significant speed boost in deep neural network computations compared to the von Neumann architecture, it is essential to develop synaptic devices with optimal performance for fully parallel vector‐matrix‐multiplication. Among various non‐volatile memory candidates, metal‐oxide based electrochemical random‐access memory (ECRAM) is considered as a promisi

In aerospace power systems, multiple power converters and multiple voltage power systems interact with each other and can result in unstable operation. When a dc-dc converter is loaded with a constant power load, it shows instability. This is because of the negative impedance characteristic of constant power load. Some poles of the converter with a constant power load are in the right half plane of the s-plane. This paper presents a compensation technique for buck converter using state space pol

Data sets involving multiple groups with shared characteristics frequently arise in practice. In this paper we extend hierarchical Dirichlet processes to model such data. Each group is assumed to be generated from a template mixture model with group level variability in both the mixing proportions and the component parameters. Variabilities in mixing proportions across groups are handled using hierarchical Dirichlet processes, also allowing for automatic determination of the number of components

Abstract Cross‐point arrays of analog synaptic devices are expected to realize neuromorphic computing hardware for neural network computations with compelling speed boost and superior energy efficiency, as opposed to the conventional hardware based on the von Neumann architecture. To achieve desired characteristics of analog synaptic devices for fully parallel vector–matrix multiplication and vector–vector outer‐product updates, metal‐oxide based electrochemical random‐access memory (ECRAM) is p