Sungjoo Yoo

To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The method generates the OS simulation models with the simulation environment as a virtual processor Since the generated OS simulation models use final OS code, the presented method can mitigate the OS code equivalence problem. The generated model also simulates different types of processor exceptions. This approach provides tw

In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component to the other part of system, we present a generic wrapper architecture that can adapt different protocols or different abstraction levels, or both. In this paper, we give a detailed explanation of applying the generic wrapper architecture to mixe

As a fast and accurate SW simulation model, we present a model called fast timed SW model. The model enables fast simulation by native execution of application SW and OS. It gives simulation accuracy by timed SW and HW simulation. When building fast timed SW models, we need to solve two problems: (1) how to enable timing synchronization between the native execution and HW simulation and (2) how to obtain the portability of native execution (that needs multi-tasking from simulation environments t

In this paper, we present thread-based optimistic distributed timed cosimulation methods which reduce the overhead of optimistic simulation. First, we present a thread simulation model to facilitate efficient distributed cosimulation. To reduce the overhead of optimistic simulation, we focus on the reduction of state saving overhead. Based on the thread simulation model, we perform thread-level state saving without saving the whole state of processor at each check-point. Especially, single check

The authors propose a bus encoding scheme which partitions the configuration data sequence of an FPGA into sub-sequences and applies partial bus-invert coding to each sub-sequence to reduce the number of data bus transitions in reconfiguring the FPGA. Experimental results show that the proposed method gives 12.79%/spl sim/17.06% more reduction of bus transitions on average compared with the conventional bus-invert coding, partial bus-invert coding, and the Beach coding.

In this paper, we explain hardware abstraction layer (HAL) and related issues in the context of SoC design. First, we give a HAL definition and examples of HAL function. HAL gives an abstraction of HW architecture to upper layer software (SW). It hides the implementation details of HW architecture, such as processor, memory management unit (MMU), cache, memory, DMA controller, timer, interrupt controller, bus/bus bridge/network interface, I/O devices, etc. HAL has been used in the conventional a

The aim is to explain the current issues of HW/SW cosimulation and to introduce a new challenge of HW/SW cosimulation for multiprocessor SoC (MPSoC). Most of the current issues are related to raising abstraction levels of HW/SW cosimulation. Mixed-level cosimulation is explained in a unified manner using a concept of ‘HW/SW interface’. First, abstraction levels in HW/SW cosimulation are explained in terms of abstraction levels of function, SW interface and HW interface. Transaction level models

In conventional multiprocessor SoC (MPSoC) design methods, we find two problems: lack of SW code portability and lack of early SW validation. The problems cause a long design cycle. To resolve them, we present a concept of two-layer hardware-dependent software (HdS). The presented HdS consists of hardware abstraction layer to abstract the sub-system architecture and SoC abstraction layer to abstract the global MPSoC architecture. During the exploration of global and sub-system architectures, the

In this paper, we present thread-based optimistic distributed timed cosimulation methods which reduce the overhead of optimistic simulation. First, we present a thread simulation model to facilitate efficient distributed cosimulation. To reduce the overhead of optimistic simulation, we focus on the reduction of state saving overhead. Based on the thread simulation model, we perform thread-level state saving without saving the whole state of processor at each check-point. Especially, single check

Thispoperpresents a concept called hierarchically grouped me.+ sage to improve the performance of geographically distributed timed cosimulation. In the proposed method, messages which are runsferred between simulators in n short period of simulated time are hierarchically grouped info a physical message to reduce the nunber of rollbacks in optimistic simulation as well as the communicadon overhead of message tranrfeer: Experiments show the eficiency of the pmposed method in an inremationnlly dis

To improve the performance of geographically distributed cosimulation, we propose a concept called hierarchically grouped message. The concept improves cosimulation performance, preserving the cosimulation accuracy, by hierarchically grouping messages transferred between simulators in a short period of simulated time into a single physical message, thereby reducing the number of physical messages. Applying the concept to hybrid and optimistic cosimulation, we can reduce the number of rollbacks a

In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component to the other part of system, we present a generic wrapper architecture that can adapt different protocols or differed abstraction levels, or both. In this paper, we give a detailed explanation of applying the generic wrapper architecture to mixed

To achieve fast verification of the software part of embedded system, we propose to run the target processor optimistically, which effectively reduces the synchronization overhead with other simulators. For the optimistic processor execution, we present a processor execution platform and state saving/restoration methods. We performed optimistic execution of ARM710A processor in the coverification of an IS-95 CDMA cellular phone system and obtained up to orders of magnitude higher performance com