[Paper Review] Floorplet: Performance-aware Floorplan Framework for Chiplet Integration

Shixin Chen, Shanyi Li+6 more|arXiv (Cornell University)|Aug 3, 2023

Interconnection Networks and SystemsComputer Science3 citations

TL;DR

Floorplet is a performance-aware floorplanning framework for chiplet-based architectures that integrates simulation-driven performance modeling with optimization for cost, reliability, and area. By leveraging Gem5-based simulation and mathematical programming, it reduces inter-chiplet communication costs by 24.81% while co-optimizing performance, reliability, and design constraints in 2.5D packaging.

ABSTRACT

A chiplet is an integrated circuit that encompasses a well-defined subset of an overall system's functionality. In contrast to traditional monolithic system-on-chips (SoCs), chiplet-based architecture can reduce costs and increase reusability, representing a promising avenue for continuing Moore's Law. Despite the advantages of multi-chiplet architectures, floorplan design in a chiplet-based architecture has received limited attention. Conflicts between cost and performance necessitate a trade-off in chiplet floorplan design since additional latency introduced by advanced packaging can decrease performance. Consequently, balancing power, performance, cost, area, and reliability is of paramount importance. To address this challenge, we propose Floorplet, a framework comprising simulation tools for performance reporting and comprehensive models for cost and reliability optimization. Our framework employs the open-source Gem5 simulator to establish the relationship between performance and floorplan for the first time, guiding the floorplan optimization of multi-chiplet architecture. The experimental results show that our framework decreases inter-chiplet communication costs by 24.81%.

Motivation & Objective

• To address the lack of EDA tools that co-optimize performance, cost, reliability, and area in chiplet-based 2.5D architectures.
• To enable realistic floorplanning using functional chiplets with complex data flow instead of abstract models.
• To model performance impact of floorplan decisions via simulation, linking physical layout to architectural performance.
• To incorporate reliability constraints such as bump stress and warpage into the floorplanning process.
• To provide a holistic framework that supports early-stage co-optimization of floorplan, performance, and technology choices.

Proposed method

• parChiplet partitions real system-on-chip (SoC) designs into functional, fabricatable chiplets with defined roles and interfaces.
• simChiplet uses the open-source Gem5 simulator to model inter-chiplet communication latency based on physical floorplan layout.
• optChiplet employs mathematical programming (e.g., Gurobi) to co-optimize floorplan under multiple constraints: performance, area, cost, and reliability.
• The framework models interposer wirelength and RDL routing delays to quantify performance impact of chiplet placement.
• Reliability constraints are encoded via equations modeling bump stress and warpage thresholds to prevent mechanical failure.
• The optimization pipeline integrates simulation feedback iteratively to refine floorplan solutions.

Experimental results

Research questions

• RQ1 How can realistic chiplet partitioning be achieved to support performance-aware floorplanning in 2.5D packaging?
• RQ2 To what extent does floorplan layout impact inter-chiplet communication latency in chiplet-based systems?
• RQ3 Can performance metrics be effectively modeled and integrated into floorplanning to reduce communication costs?
• RQ4 How can reliability constraints such as bump stress and warpage be co-optimized with performance and area in chiplet floorplanning?
• RQ5 What is the trade-off between performance, cost, and reliability in multi-chiplet floorplanning, and how can it be systematically balanced?

Key findings

• The Floorplet framework reduces inter-chiplet communication costs by 24.81% compared to baseline approaches.
• Performance-aware floorplanning significantly improves system throughput by minimizing inter-chiplet latency through optimized placement.
• The integration of Gem5-based simulation enables accurate performance modeling of floorplan decisions in real chiplet architectures.
• Mathematical programming with Gurobi solver achieves optimal or near-optimal solutions within acceptable time for 10–30 chiplet designs (20 min to 10 hours depending on scale).
• The framework successfully incorporates complex reliability constraints such as bump stress and warpage thresholds into the floorplanning process, which prior works often ignore.
• Ignoring performance metrics in floorplanning leads to measurable performance degradation, validating the necessity of early performance-driven optimization.