[Paper Review] Floorplanning and topology generation for application-specific network-on-chip

Bei Yu, Sheqin Dong+2 more|arXiv (Cornell University)|Jan 18, 2010

Interconnection Networks and Systems15 references42 citations

TL;DR

This paper proposes a two-phase framework for application-specific network-on-chip (NoC) topology generation: first, partition-driven floorplanning optimizes component placement, followed by a hybrid heuristic and min-cost max-flow approach to insert switches and network interfaces while minimizing power consumption through path allocation. The method achieves significant power savings in experimental evaluations.

ABSTRACT

Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

Motivation & Objective

• Address the challenge of designing power-efficient, application-specific NoC topologies for complex system-on-chip architectures.
• Reduce power consumption in NoC designs by optimizing switch placement and communication path allocation.
• Integrate floorplanning with topology synthesis to improve area and power efficiency in NoC design flow.
• Develop a scalable and effective method for generating customized NoC topologies tailored to specific application workloads.

Proposed method

• Apply partition-driven floorplanning to group functional modules based on communication patterns, reducing inter-module communication overhead.
• Use a heuristic method to determine optimal switch insertion points in the post-floorplanning phase to improve connectivity and reduce latency.
• Employ a min-cost max-flow algorithm to model and solve the network interface and switch placement problem with power minimization as the objective.
• Allocate communication paths using the min-cost max-flow solution to ensure low-power data transmission between components.
• Integrate path allocation with switch and network interface placement to jointly minimize total power consumption.
• Ensure the final topology is both routable and power-efficient by combining floorplanning with topology synthesis in a unified framework.

Experimental results

Research questions

• RQ1 How can floorplanning be effectively integrated with NoC topology generation to improve power efficiency?
• RQ2 What is the impact of switch and network interface placement on overall NoC power consumption?
• RQ3 Can a combination of heuristic methods and min-cost max-flow algorithms effectively generate low-power NoC topologies?
• RQ4 How does the proposed two-phase approach compare to conventional NoC design flows in terms of power and area efficiency?

Key findings

• The proposed two-phase framework effectively reduces power consumption in application-specific NoC designs.
• The integration of partition-driven floorplanning with topology synthesis leads to improved communication efficiency and reduced inter-module latency.
• The use of min-cost max-flow for switch and interface placement enables optimal path allocation with minimal energy cost.
• The experimental results confirm that the method achieves significant power savings compared to baseline approaches.