[论文解读] Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review

Luigi Capogrosso, Pietro Bonazzi+1 more|arXiv (Cornell University)|Feb 18, 2026

Advanced Memory and Neural Computing被引用 0

一句话总结

本论文综述超低功耗边缘AI处理器并在GAP9、STM32N6与索尼IMX500上基准PicoSAM2，以比较延迟、MAC/时钟、MAC/能源、以及能耗-延时乘积（EDP）。

ABSTRACT

This review examines the rapidly evolving landscape of ultra-low-power edge processors, covering heterogeneous Systems-on-Chips (SoCs), neural accelerators, near-sensor and in-sensor architectures, and emerging dataflow and memory-centric designs. We categorize commercially available and research-grade platforms according to their compute paradigms, power envelopes, and memory hierarchies, and analyze their suitability for always-on and latency-critical Artificial Intelligence (AI) workloads. To complement the architectural overview with empirical evidence, we benchmark a 336 million Multiply-Accumulate (MAC) segmentation model (PicoSAM2) on three representative processors: GAP9, leveraging a multi-core RISC-V architecture augmented with hardware accelerators; the STM32N6, which pairs an advanced ARM Cortex-M55 core with a dedicated neural architecture accelerator; and the Sony IMX500, representing in-sensor stacked-Complementary Metal-Oxide-Semiconductor (CMOS) compute. Collectively, these platforms span MCU-class, embedded neural accelerator, and in-sensor paradigms. The evaluation reports latency, inference efficiency, energy efficiency, and energy-delay product. The results show a clear divergence in hardware behavior, with the IMX500 achieving the highest utilization (86.2 MAC/cycle) and the lowest energy-delay product, highlighting the growing significance and technological maturity of in-sensor processing. GAP9 offers the best energy efficiency within microcontroller-class power budgets, and the STM32N6 provides the lowest raw latency at a significantly higher energy cost. Together, the review and benchmarks provide a unified view of the current design directions and practical trade-offs that are shaping the next generation of ultra-low-power and in-sensor AI processors.

研究动机与目标

• 由于边缘的延迟、隐私和感知需求，需要在设备端实现能效AI的动机。
• 描绘超低功耗边缘处理器的全景，包括MCU级别、嵌入式加速器与感知内计算。
• 提供实证基准测试，揭示不同架构在真实工作负载下的设计折中。
• 为面向常时运行与低延迟AI工作负载的架构选择提供指导。

提出的方法

• 按计算范式、功耗包络和存储层次结构，对商用与研究级边缘AI平台进行调研。
• 在三款处理器（GAP9、STM32N6、IMX500）上，对336 MMAC的PicoSAM2分割模型进行循环精确分析的基准并进行功耗测量。
• 评估四个以硬件为中心的指标：每次推断的延迟、MAC/时钟、MAC/J，以及能耗-延迟乘积（EDP）。
• 报告在利用率、数据流效率和跨体系结构的内存瓶颈方面的定性与定量洞察。

Figure 1: Peak performance in TOPS vs. power consumption of publicly announced AI accelerators and processors. Data are from [ 10 , 11 , 12 , 13 ] .

实验结果

研究问题

• RQ1 在运行一个具有代表性的分割模型时，异构超低功耗边缘处理器的实际性能与能效特性如何？
• RQ2 感知内、MCU级与嵌入式神经加速器在利用率、延迟、每推断能耗与EDP方面的对比如何？
• RQ3 哪些架构因素（内存层次、数据流、数据移动）在200 mW以下预算下对设备端AI性能的影响最大？

主要发现

HW Platform	Peak Perf. (TOPS)	Power (W)	Precision	HW Architecture	Efficiency (TOPS/W)
Netcast	1.00E+01	0.001	int8	Dataflow ASIC	1.00E+04
Ergo	4.00E+00	0.073	int8	Tensor ASIC	5.48E+01
Ethos N77	4.10E+00	0.800	int8	Tensor ASIC	5.13E+00
MX3	5.00E+00	1.000	fp16	Manycore ASIC	5.00E+00
Tianjic	1.21E+00	0.950	int8	Neuromorphic	1.27E+00
AML200	2.00E+00	0.100	int8	Analog In-Memory	2.00E+01
GAP9	1.51E-01	0.0640	int8	RISC-V Manycore	2.36E+00
AIStorm	2.50E+00	0.225	int8	Analog Compute-in-Sensor	1.11E+01
Gyrfalcon	2.80E+00	0.224	int8	Manycore ASIC	1.25E+01
AML100	4.00E-01	0.020	int8	Analog In-Memory	2.00E+01
STM32N6	6.00E-01	0.200	int8	ARM Cortex-M55 + NPU	3.00E+00
Cortex-M85 (STM32V8/RA8)	1.30E-01	0.250	int8	ARM Cortex-M85	5.20E-01
NDP101	2.00E-01	0.010	int4	RISC-V + HW Acc	2.00E+01
NDP200	6.20E-03	0.010	int8	RISC-V + HW Acc	6.20E-01
NDP250	3.00E-02	0.100	int8	RISC-V + HW Acc	3.00E-01
IMX500	7.952E-02	0.016	int8	Manycore ASIC	4.97E+00
Max 78000	5.60E-02	0.028	int8	Tensor Accelerator MCU	2.00E+00
GAP8	2.27E-02	0.100	int8	RISC-V Manycore	2.27E-01
Eyeriss	6.72E-02	0.278	int16	Dataflow ASIC	2.42E-01
ShiDianNao	1.94E-01	0.320	int16	Dataflow ASIC	6.06E-01
DianNao	4.52E-01	0.485	int16	Dataflow ASIC	9.32E-01
PuDianNao	1.06E+00	0.596	int16	Dataflow ASIC	1.78E+00
EIE	1.02E-01	0.600	int16	Dataflow ASIC (Sparse)	1.70E-01
K210	2.50E-01	0.300	int8	RISC-V Dual Core + KPU	8.33E-01
Kendrite K210	2.30E-01	0.300	int8	RISC-V Dual Core + KPU	7.67E-01
TrueNorth	1.89E+00	0.500	int8	Neuromorphic	3.78E+00
KL520 NPU	3.00E-01	0.500	int8	Tensor ASIC	6.00E-01
xcore.ai	5.12E-02	1.000	int8	DSP-like Multicore	5.12E-02
KL720	1.40E+00	1.556	int8	Tensor ASIC	9.00E-01

• IMX500在测试平台中实现最高的计算密度，达到86.2 MAC/时钟，并且在能耗-延迟乘积方面为最低。
• GAP9在MCU级功耗预算下依然提供具有竞争力的MAC/J，强调在低频下的能效。
• STM32N6提供最低的原始延迟（13.7 ms），但伴随显著更高的能耗。
• IMX500在能效方面表现优越（MAC/J为1359.6 MMAC/J），这得益于其感知内计算设计的驱动。
• GAP9在面向电池受限的MCU级部署中仍具竞争力；STM32N6以低延迟为导向，能耗较高；IMX500展示了感知内处理的优势。
• 基准测试凸显了边缘、近传感与传感内架构之间的不同设计取舍。

Figure 2: Benchmarking results of PicoSAM2 [ 25 ] , comparing its energy efficiency, latency, inference efficiency, and energy–delay product (EDP) on GAP9, STM32N6, and IMX500. The results highlight the advantages of in-sensor compute for improved energy efficiency and latency.