[论文解读] Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.

Donghyuk Lee, Samira Khan+6 more|arXiv (Cornell University)|Oct 30, 2016

Parallel Computing and Optimization Techniques参考文献 82被引用 12

一句话总结

本文识别并利用了现代DRAM芯片中由设计引起的访问延迟差异——即靠近外围电路的存储单元可被更快访问——通过开发两种低成本机制，动态发现并利用每个区域的最低可靠工作延迟。该方法在不降低可靠性的前提下，将DRAM访问延迟降低高达25%，通过硬件感知的内存访问优化提升了系统性能。

ABSTRACT

Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several prior forms of this variation, such as manufacturing-process- or temperature-induced variation. We empirically observe a new form of variation that exists within a DRAM chip, induced by the design and placement of different components in the DRAM chip, where different regions in DRAM, based on their relative distance from the peripheral structures, require different minimum access latencies for reliable operation. In particular, cells closer to the peripheral structures can be accessed much faster than cells that are farther. We call this phenomenon design-induced variation in DRAM. Our goal, in this work, is to understand and exploit design-induced variation to develop low-cost mechanisms to dynamically find and use the lowest latency a DRAM chip can reliably operate at and thus improve overall system performance while ensuring reliable system operation. To this end, we first experimentally demonstrate and analyze designed-induced variation in modern DRAM devices by testing and characterizing 96 DIMMs (768 DRAM chips). Our characterization identifies DRAM regions that are vulnerable to errors, if operated at lower latency, and finds consistency in their locations across a given DRAM chip generation, due to design-induced variation. Based on our experimental analysis, we develop two mechanisms that reliably reduce DRAM latency.

研究动机与目标

• 调查并表征由组件物理布局引起的DRAM芯片中此前未被探索的延迟差异形式。
• 理解设计引起的延迟差异如何影响DRAM芯片不同区域的最小可靠访问延迟。
• 开发低成本、动态的机制，以识别并利用每个DRAM区域的最低可能延迟，确保可靠运行。
• 通过区域特定的延迟调节，减少DRAM延迟，同时保持可靠性，从而提升整体系统性能。

提出的方法

• 通过实测分析96根DIMM（共768个DRAM芯片）中的延迟差异，识别出具有不同最小访问延迟的区域。
• 基于DRAM芯片中靠近外围结构的程度，映射延迟敏感区域的空间分布。
• 设计并实现两种动态机制，在运行时检测并适应每个DRAM区域的最低可靠延迟。
• 通过区域特定的延迟调节，使靠近外围电路的存储单元获得更快访问，从而利用设计引起的延迟差异。
• 通过基于实验表征的最小延迟阈值，确保每个区域的运行不低于是其最小安全延迟，从而保障可靠性。

实验结果

研究问题

• RQ1 DRAM芯片内部组件的物理布局在多大程度上影响存储单元的最小可靠访问延迟？
• RQ2 在同代DRAM芯片中，设计引起的延迟差异在多大程度上具有一致性？
• RQ3 动态的、区域感知的延迟调节能否在不损害可靠性的前提下降低整体DRAM访问延迟？
• RQ4 在不同芯片区域以低于标称延迟的速率运行DRAM单元时，性能与可靠性之间存在何种权衡？

主要发现

• 设计引起的延迟差异存在于DRAM芯片中，靠近外围结构的存储单元需要显著更低的访问延迟才能实现可靠操作。
• 由于设计布局固定，同代DRAM芯片中延迟敏感区域的位置具有一致性。
• 所提出的机制相比标称工作延迟，将DRAM访问延迟降低了高达25%。
• 通过确保每个区域的运行延迟不低于其最小安全阈值，机制有效维持了系统可靠性。
• 该方法成本低廉，能够动态适应芯片的实际运行条件，实现无需硬件重构的性能提升。