[论文解读] Reducing End-to-End Latency of Cause-Effect Chains with Shared Cache Analysis

Yixuan Zhu, Yinkang Gao+9 more|arXiv (Cornell University)|Jan 28, 2026

Real-Time Systems Scheduling被引用 0

一句话总结

该论文提出一个时间敏感的、块级共享缓存分析框架（TSC），将调度信息整合以计算多链因果系统在具有共享缓存的多核平台上的更紧的WCET和端到端延迟。在某些设置下，端到端延迟可减少最多34%（双核）和26%（四核）。

ABSTRACT

Cause-effect chains, as a widely used modeling method in real-time embedded systems, are extensively applied in various safety-critical domains. End-to-end latency, as a key real-time attribute of cause-effect chains, is crucial in many applications. But the analysis of end-to-end latency for cause-effect chains on multicore platforms with shared caches still presents an unresolved issue. Traditional methods typically assume that the worst-case execution time (WCET) of each task in the cause-effect chain is known. However, in the absence of scheduling information, these methods often assume that all shared cache accesses result in misses, leading to an overestimation of WCET and, consequently, affecting the accuracy of end-to-end latency. However, effectively integrating scheduling information into the WCET analysis process of the chains may introduce two challenges: first, how to leverage the structural characteristics of the chains to optimize shared cache analysis, and second, how to improve analysis accuracy while avoiding state space explosion. To address these issues, this paper proposes a novel end-to-end latency analysis framework designed for multi-chain systems on multicore platforms with shared caches. This framework extracts scheduling information and structural characteristics of cause-effect chains, constructing fine-grained and scalable inter-core memory access contexts at the basic block level for time-sensitive shared cache analysis. This results in more accurate WCET (TSC-WCET) estimates, which are then used to derive the end-to-end latency. Finally, we conduct experiments on dual-core and quad-core systems with various cache configurations, which show that under certain settings, the average maximum end-to-end latency of cause-effect chains is reduced by up to 34% and 26%.

研究动机与目标

• 利用调度信息与链结构改进因果链的共享缓存分析。
• 在基础块级别提供可扩展的、细粒度的跨核内存访问上下文。
• 通过避免过于保守的缓存干扰假设来降低延迟乐观性。
• 开发一个安全、集成的框架，为多链系统提供更紧的端到端延迟估计。

提出的方法

• 构建一个两阶段分析框架：先得到跨核的架构无关的基于调度的任务序列，然后进行架构相关的细粒度共享缓存干扰分析。
• 用相对时间和区间化时间来表示基础块和循环，以推导相对于系统启动的绝对执行时间。
• 使用包含改进的CHMC（缓存命中/未命中分类）与跨核上下文和干扰计数的ILP模型来计算每个任务的TSC-WCET。
• 在任务实例、循环和基础块之间进行分层干扰分析，并通过互斥信息来剪枝不可行的干扰。
• 通过回连TT链或同周期TT链将链路合并，以确保每个核只有一个确定的作业序列，从而降低状态空间复杂度。
• 提供形式化的安全性证明，确保在跨核干扰建模下端到端延迟保持安全。

实验结果

研究问题

• RQ1 如何将来自因果链的调度信息整合到共享缓存分析中以降低WCET乐观性？
• RQ2 如何利用因果链的结构特征来创建细粒度、可扩展的跨核内存访问上下文？
• RQ3 在基础块级别采用相对和区间化时间模型是否能获得更紧的CHMC估计和改进的端到端延迟界限？
• RQ4 在多核共享缓存分析中，哪些方法可以在不牺牲安全性的前提下降低干扰高估？
• RQ5 所提框架对双核和四核在不同缓存配置下的端到端延迟有何影响？

主要发现

• 在某些设置下，双核系统的平均最大端到端延迟可减少至多34%。
• 在某些设置下，四核系统的平均最大端到端延迟可减少至多26%。