[Paper Review] T-count Optimized Quantum Circuits for Bilinear Interpolation

Edgard Muñoz‐Coreas, Himanshu Thapliyal|arXiv (Cornell University)|Sep 24, 2018

Quantum Computing Algorithms and Architecture15 references4 citations

TL;DR

This paper presents T-count optimized quantum circuits for bilinear interpolation in NEQR-encoded images using Clifford+T gates. By replacing costly quantum division circuits with a novel register management technique and employing efficient quantum adder, subtractor, and multiplier circuits, the proposed design achieves a 92.52% reduction in T-count for both scale-up and scale-down operations compared to prior work.

ABSTRACT

Quantum circuits for basic image processing functions such as bilinear interpolation are required to implement image processing algorithms on quantum computers. In this work, we propose quantum circuits for the bilinear interpolation of NEQR encoded images based on Clifford+T gates. Quantum circuits for the scale up operation and scale down operation are illustrated. The proposed quantum circuits are based on quantum Clifford+T gates and are optimized for T-count. Quantum circuits based on Clifford+T gates can be made fault tolerant but the T gate is very costly to implement. As a result, reducing T-count is an important optimization goal. The proposed quantum bilinear interpolation circuits are based on (i) a quantum adder, (ii) a proposed quantum subtractor, and (iii) a quantum multiplication circuit. Further, both designs are compared and shown to be superior to existing work in terms of T-count. The proposed quantum bilinear interpolation circuits for the scale down operation and for the scale up operation each have a $92.52\%$ improvement in terms of T-count compared to the existing work.

Motivation & Objective

• To address the high T-count cost of existing quantum bilinear interpolation circuits for NEQR-encoded images.
• To reduce the resource overhead of quantum arithmetic operations in image processing circuits.
• To design fault-tolerant quantum circuits using only Clifford+T gates for scalable quantum image processing.
• To eliminate the need for quantum division circuits, which are particularly expensive in T-count.
• To achieve significant improvements in T-count and functional block count over existing designs.

Proposed method

• The proposed design uses a quantum adder with T-count of $4n$, a novel quantum subtractor with T-count of $4n - 4$, and a quantum multiplier with T-count of $8n^2 - 4n$.
• The method avoids quantum division by not assigning the least significant $2m-1$ to $0$ bits of the result register to the output pixel color qubit, thereby eliminating the need for division circuits.
• Functional blocks are carefully laid out to reduce the number of required arithmetic units, including a reduction from 4 to 2 quantum subtractor circuits.
• The design leverages Clifford+T gate implementations of temporary logical-AND and uncomputation gates to construct Toffoli gates and support arithmetic operations.
• The circuits are constructed using only Clifford+T gates to ensure fault tolerance and compatibility with surface codes.
• T-count is computed by summing the T-counts of each functional block multiplied by their usage frequency in the circuit.

Experimental results

Research questions

• RQ1 Can quantum bilinear interpolation circuits for NEQR images be optimized to reduce T-count while maintaining correctness?
• RQ2 Is it possible to eliminate quantum division circuits in bilinear interpolation without compromising functionality?
• RQ3 How can quantum arithmetic components be redesigned to minimize T-count in image processing circuits?
• RQ4 What is the achievable T-count improvement when replacing division with register management in quantum bilinear interpolation?
• RQ5 Can a combination of efficient adder, subtractor, and multiplier circuits yield superior performance in terms of T-count and resource usage?

Key findings

• The proposed quantum bilinear interpolation circuit for the scale-up operation achieves a 92.52% improvement in T-count compared to the existing design in [5].
• The proposed design eliminates the need for quantum division circuits, which were a major contributor to high T-count in prior work.
• The number of quantum subtraction circuits is reduced from 4 to 2, contributing to lower overall resource usage.
• The T-count of the proposed design is $64n^2 - 12n - 8$, compared to $856n^2 + 196n - 98 + 8\sum_{i=1}^{\log_2(n)} \frac{n}{2^i}(14(n+i-2^{i-1}) - 14)$ in the existing work.
• The proposed quantum adder, subtractor, and multiplier circuits are all optimized for low T-count, with the subtractor achieving $4n - 4$ T-gates.
• The proposed circuits are fully compatible with fault-tolerant quantum computing via the Clifford+T gate set, enabling scalable and reliable implementation.