Ewha Womans University · Engineering
Professor Seongjae Cho's research lab specializes in next-generation semiconductor devices and advanced nanomaterials for high-performance, low-power electronics and energy storage. The lab focuses on innovative transistor architectures such as junctionless nanowire FETs, gate-all-around tunneling FETs, and Ge/GaAs heterojunction TFETs, emphasizing their radio-frequency and high-frequency performance through advanced simulation and modeling. It also explores sustainable energy solutions using biowaste-derived nanomaterials, particularly for supercapacitors, aiming to develop eco-friendly and cost-effective energy storage systems. The lab bridges fundamental device physics with practical applications in digital electronics, optoelectronics, and green energy technologies.
Figures are computed from collected data and may differ slightly.
Two-dimensional materials have garnered interest from the perspectives of physics, materials, and applied electronics owing to their outstanding physical and chemical properties. Advances in exfoliation and synthesis technologies have enabled preparation and electrical characterization of various atomically thin films of semiconductor transition metal dichalcogenides (TMDs). Their two-dimensional structures and electromagnetic spectra coupled to bandgaps in the visible region indicate their suit
The small-signal parameters of gate-all-around tunneling field-effect transistors (GAA TFETs) with different gate lengths were extracted and analyzed in terms of their gate capacitance, source-drain conductance, transconductance, distributed channel resistance, and inversion layer length. Because of the unique current drive and inversion layer formation mechanisms of a TFET compared to a conventional MOSFET, the gate-bias dependence values of the primary small-signal parameters of a GAA TFET als
Nanocomposites are gaining high demand for the development of next-generation energy storage devices because of their eco-friendly and cost-effective natures. However, their short-term energy retainability and marginal stability are regarded as hindrances to overcome. In this work, we demonstrate a high-performance supercapacitor fabricated by biocarbon-based MoS<sub>2</sub> (Bio-C/MoS<sub>2</sub>) nanoparticles synthesized by a facile hydrothermal approach using date fruits. Here, we report the
In this study, we propose and characterize by simulation a silicon-compatible compound semiconductor tunneling field-effect transistor (TFET) based on germanium (Ge)/gallium arsenide (GaAs) heterojunction aiming the various integrated systems on silicon substrate. By introducing Ge as p+ source and GaAs as the high-mobility channel and n+ drain materials, we maximize on-state current (Ion) and minimize off-state current (Ioff) to obtain a TFET for high performance and low standby power capabilit
The motivation for driving semiconductor devices can be found in the development of advanced computers which can contribute to the betterment in our daily lives. The contribution has been largely made by semiconductor logic devices traveling the pavements identified as technology nodes for device shrinkage that enables high-speed and low-power operations. Lighter and faster processors are the everlasting goals in electronics and computer science, and have been concerned with logic technologies.
This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping th
Non-von-Neumann computer architecture is gaining a great deal of interest for eliminating the speed bottleneck in transferring data between the processing and memory units by improving the processing parallelism. Hardware-driven neuromorphic systems are pursued actively for this goal, and they should accompany the innovations in the hardware components for higher energy efficiency. In this work, an indium gallium zinc oxide (IGZO)-based synaptic device was developed, and its synaptic behaviors w
Abstract To efficiently develop an extremely intensive storage memory, the resistive random‐access memory (RRAM), which operates by producing and rupturing conductive filaments, is essential. However, due to the stochastic nature of filament production, this filamentary type resistive switching has an inherent limitation, which entails the unpredictability of the driving voltage and resistance states. Several strategies such as doping, research into multilayer stacks, and interface engineering,
Metal-oxide nanomaterials have attracted great interest in recent years due to their novel characteristics such as surface effect and quantum confinement. A fascinating Au nanorod (NR)/cuprous oxide core-shell composite (AuNR/Cu<sub>2</sub>O) was directly synthesized using a moderate one-pot facile green redox method and further utilized for energy storage applications in a supercapacitor. The synthesis mechanism is based on the use of reducing agents to form the core shell. The resultant compos
In this work, a study on a semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) in the SFGST, a poly-Si semi-floating gate (SFG) and a SiN charge-trap layer are utilized, respectively. When an adequate number of holes are accumulated in the SFG, they are injected into the nitride charge-trap layer by the Fowler⁻Nordheim tunneling mechanism. Mor
In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read d
Open papers in the app to read, cite, and organize with AI.